ebafc595
 csaad
mise à jour fichi...
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Release 14.3 Map P.40xd (nt64)
Xilinx Map Application Log File for Design 'FPGA_projet'
Design Information
------------------
Command Line : map -p XC3S1500-FG676-4 -pr b -tx off -c 100 -t 1 -u
-ignore_keep_hierarchy -o fpga_projet_map.ncd fpga_projet.ngd
Target Device : xc3s1500
Target Package : fg676
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Wed May 17 18:19:11 2017
WARNING:Map:124 - The command line option -t can only be used when running in
timing mode (-timing option). The option will be ignored.
WARNING:Map:210 - The -tx switch is not supported for this architecture, and
will be ignored.
Mapping design into LUTs...
WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_n2j/n2j" (output signal=n2j) has a mix of clock and
non-clock loads. The non-clock loads are:
Pin I0 of U3/U_FREQ/freq_sig_m2_am
Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clkd
Pin I0 of U3/U_FREQ/divisor_5_0_component_c0/clko
Writing file fpga_projet_map.ngm...
Running directed packing...
WARNING:Pack:266 - The function generator U5/TAP1/tapstate_r__not_0 failed to
merge with F5 multiplexer U5/TAP1/i223. Tried to combine two collections of
symbols from different positions within the same layer. The design will
exhibit suboptimal timing.
WARNING:Pack:266 - The function generator U5/TAP1/tapstate_r__not_0 failed to
merge with F5 multiplexer U5/TAP1/i224. Unable to resolve the conflicts
between two or more collections of symbols which have restrictive placement
or routing requirements. The original symbols are:
MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237)
LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal =
U5/TAP1/tapstate_r__not_0)
MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235)
Failure 1: Unable to combine the following symbols into a single slice.
MUXF5 symbol "U5/TAP1/i224" (Output Signal = U5/TAP1/n237)
MUXF5 symbol "U5/TAP1/i222" (Output Signal = U5/TAP1/n235)
LUT symbol "U5/TAP1/tapstate_r__not_0" (Output Signal =
U5/TAP1/tapstate_r__not_0)
There is more than one F5MUX.
Failure 2: Unable to combine the following symbols into a single slice.
MUXF6 symbol "U5/TAP1/i227" (Output Signal = U5/TAP1/n240)
MUXF5 symbol "U5/TAP1/i225" (Output Signal = U5/TAP1/n238)
MUXF6 symbol "U5/TAP1/i226" (Output Signal = U5/TAP1/n239)
MUXF5 symbol "U5/TAP1/i223" (Output Signal = U5/TAP1/n236)
There is more than one MUXF6.
The design will exhibit suboptimal timing.
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Writing design file "fpga_projet_map.ncd"...
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c9 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c10 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c1 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c4 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c5 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c3 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c7 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c8 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c6 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c0 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net U3/U_FREQ/clk_div_c2 is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
U3/U_FREQ/divisor_9_0_component_c8/u1_s is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
U3/U_FREQ/divisor_25_0_component_c9/u1_s is sourced by a combinatorial pin.
This is not good design practice. Use the CE pin to control the loading of
data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U8_TC is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net PinSignal_U3_FREQ is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <U3/TDO_ENABLE> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/exit1dr> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_21> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_20> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_23> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_22> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_31> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_30> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_17> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_16> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_25> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_24> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_19> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_18> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_27> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_26> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_29> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_28> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/TAP1/reset> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_11> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_10> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_13> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_12> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_15> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_14> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U7/CEO> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Length/regout_8> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterInput_Value/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterConfiguration/regout_8> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_1> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_0> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_3> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_2> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_5> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_4> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_7> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_6> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_9> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <U5/RegisterOutput_Length/regout_8> is
incomplete. The signal does not drive any load pins in the design.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 463 out of 26,624 1%
Number of 4 input LUTs: 437 out of 26,624 1%
Logic Distribution:
Number of occupied Slices: 343 out of 13,312 2%
Number of Slices containing only related logic: 343 out of 343 100%
Number of Slices containing unrelated logic: 0 out of 343 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 449 out of 26,624 1%
Number used as logic: 437
Number used as a route-thru: 12
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 7 out of 487 1%
IOB Flip Flops: 2
Number of BUFGMUXs: 2 out of 8 25%
Average Fanout of Non-Clock Nets: 3.01
Peak Memory Usage: 281 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "fpga_projet_map.mrp" for details.
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