ebafc595
 csaad
mise à jour fichi...
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Release 14.3 par P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
ALTIUM-07:: Wed May 17 18:19:15 2017
par -w -t 1 fpga_projet_map.ncd fpga_projet.ncd
"C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default -
All Constraints\FPGA_projet_map.pcf"
Constraints file: C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All
Constraints\FPGA_projet_map.pcf.
Loading device for application Rf_Device from file '3s1500.nph' in environment C:\Xilinx\14.3\ISE_DS\ISE\.
"FPGA_projet" is an NCD, version 3.2, device xc3s1500, package fg676, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.39 2012-10-12".
Device Utilization Summary:
Number of BUFGMUXs 2 out of 8 25%
Number of External IOBs 7 out of 487 1%
Number of LOCed IOBs 7 out of 7 100%
Number of Slices 343 out of 13312 2%
Number of SLICEMs 0 out of 6656 0%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 1 secs
Finished initial Timing Analysis. REAL time: 1 secs
WARNING:Par:288 - The signal U3/TDO_ENABLE has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/TAP1/exit1dr has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_11 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_10 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_13 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_12 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_21 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_20 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_15 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_14 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_23 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_22 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_31 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_30 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_17 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_16 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_25 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_24 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_19 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_18 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_27 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_26 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_29 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_28 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_11 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_10 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_13 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_12 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_15 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_14 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/TAP1/reset has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_11 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_10 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_13 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_12 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_15 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_14 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U7/CEO has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_1 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_0 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_3 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_2 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_5 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_4 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_7 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_6 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_9 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Length/regout_8 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterInput_Value/regout_0 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_1 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_0 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_3 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_2 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_5 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_4 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_7 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_6 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_9 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterConfiguration/regout_8 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_1 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_0 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_3 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_2 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_5 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_4 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_7 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_6 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_9 has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal U5/RegisterOutput_Length/regout_8 has no load. PAR will not attempt to route this signal.
Starting Placer
Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:7607b0db) REAL time: 2 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:7607b0db) REAL time: 2 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:7607b0db) REAL time: 2 secs
Phase 4.2 Initial Clock and IO Placement
...........................
WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <n2k> is placed at site <BUFGMUX0>. The IO component <JTAG_NEXUS_TCK> is placed
at site <P21>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an
ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <JTAG_NEXUS_TCK.PAD> allowing your design to
continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override
is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design.
Phase 4.2 Initial Clock and IO Placement (Checksum:c9614ebb) REAL time: 3 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:c9614ebb) REAL time: 3 secs
Phase 6.8 Global Placement
.....
....
...........................
.................
...........................
Phase 6.8 Global Placement (Checksum:ad8fab58) REAL time: 4 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:ad8fab58) REAL time: 4 secs
Phase 8.18 Placement Optimization
Phase 8.18 Placement Optimization (Checksum:79fd03f7) REAL time: 5 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:79fd03f7) REAL time: 5 secs
Total REAL time to Placer completion: 5 secs
Total CPU time to Placer completion: 5 secs
Writing design to file fpga_projet.ncd
Starting Router
Phase 1 : 1948 unrouted; REAL time: 5 secs
Phase 2 : 1693 unrouted; REAL time: 6 secs
Phase 3 : 250 unrouted; REAL time: 6 secs
Phase 4 : 333 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs
Updating file: fpga_projet.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 8 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 12 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 12 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 12 secs
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c9 may have excessive skew because
0 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:n2j may have excessive skew because
0 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c10 may have excessive skew because
1 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c1 may have excessive skew because
0 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c4 may have excessive skew because
0 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c5 may have excessive skew because
0 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c3 may have excessive skew because
2 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c7 may have excessive skew because
0 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c8 may have excessive skew because
2 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c6 may have excessive skew because
2 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c0 may have excessive skew because
0 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/clk_div_c2 may have excessive skew because
0 CLK pins and 2 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/divisor_9_0_component_c8/u1_s may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:U3/U_FREQ/divisor_25_0_component_c9/u1_s may have excessive skew because
2 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:PinSignal_U8_TC may have excessive skew because
2 CLK pins and 3 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 12 secs
Total CPU time to Router completion: 12 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| n2j | BUFGMUX1| No | 11 | 0.223 | 1.071 |
+---------------------+--------------+------+------+------------+-------------+
| n2k | BUFGMUX0| No | 211 | 0.409 | 1.231 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c9 | | | | | |
| | Local| | 19 | 0.161 | 3.547 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c1 | | | | | |
| 0 | Local| | 2 | 0.000 | 0.697 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c1 | | | | | |
| | Local| | 5 | 0.000 | 2.467 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c4 | | | | | |
| | Local| | 5 | 0.000 | 0.849 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c5 | | | | | |
| | Local| | 5 | 0.000 | 2.282 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c3 | | | | | |
| | Local| | 5 | 0.000 | 1.497 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c7 | | | | | |
| | Local| | 6 | 0.000 | 0.873 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c8 | | | | | |
| | Local| | 6 | 0.638 | 1.364 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c6 | | | | | |
| | Local| | 5 | 0.006 | 1.034 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c0 | | | | | |
| | Local| | 4 | 0.000 | 0.517 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/clk_div_c2 | | | | | |
| | Local| | 4 | 0.000 | 2.055 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/divisor_9_ | | | | | |
| 0_component_c8/u1_s | Local| | 3 | 0.000 | 1.372 |
+---------------------+--------------+------+------+------------+-------------+
|U3/U_FREQ/divisor_25 | | | | | |
|_0_component_c9/u1_s | | | | | |
| | Local| | 3 | 0.000 | 1.397 |
+---------------------+--------------+------+------+------------+-------------+
| PinSignal_U8_TC | Local| | 5 | 0.000 | 0.719 |
+---------------------+--------------+------+------+------------+-------------+
| PinSignal_U3_FREQ | Local| | 6 | 0.060 | 3.995 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 9.683ns| N/A| 0
U_FREQ/clk_div_c9 | HOLD | 1.311ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net n2j | SETUP | N/A| 6.744ns| N/A| 0
| HOLD | 0.961ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net n2k | SETUP | N/A| 14.852ns| N/A| 0
| HOLD | 0.534ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 1.673ns| N/A| 0
U_FREQ/clk_div_c10 | HOLD | 0.893ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.085ns| N/A| 0
U_FREQ/clk_div_c1 | HOLD | 0.883ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 1.805ns| N/A| 0
U_FREQ/clk_div_c4 | HOLD | 0.893ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.356ns| N/A| 0
U_FREQ/clk_div_c5 | HOLD | 0.914ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.348ns| N/A| 0
U_FREQ/clk_div_c3 | HOLD | 0.916ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 1.890ns| N/A| 0
U_FREQ/clk_div_c7 | HOLD | 0.939ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.613ns| N/A| 0
U_FREQ/clk_div_c8 | HOLD | 0.603ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.161ns| N/A| 0
U_FREQ/clk_div_c6 | HOLD | 0.797ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.009ns| N/A| 0
U_FREQ/clk_div_c0 | HOLD | 1.033ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 1.861ns| N/A| 0
U_FREQ/clk_div_c2 | HOLD | 0.889ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 1.902ns| N/A| 0
U_FREQ/divisor_9_0_component_c8/u1_s | HOLD | 0.894ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net U3/ | SETUP | N/A| 2.244ns| N/A| 0
U_FREQ/divisor_25_0_component_c9/u1_s | HOLD | 0.700ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Pin | SETUP | N/A| 2.121ns| N/A| 0
Signal_U8_TC | HOLD | 1.030ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Pin | SETUP | N/A| 2.391ns| N/A| 0
Signal_U3_FREQ | HOLD | 0.580ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 69 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 14 secs
Total CPU time to PAR completion: 13 secs
Peak Memory Usage: 316 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 87
Number of info messages: 1
Writing design to file fpga_projet.ncd
PAR done!
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