.model Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_32_

  .inputs Rst

  .inputs ResetValue<31>

  .inputs ResetValue<30>

  .inputs ResetValue<29>

  .inputs ResetValue<28>

  .inputs ResetValue<27>

  .inputs ResetValue<26>

  .inputs ResetValue<25>

  .inputs ResetValue<24>

  .inputs ResetValue<23>

  .inputs ResetValue<22>

  .inputs ResetValue<21>

  .inputs ResetValue<20>

  .inputs ResetValue<19>

  .inputs ResetValue<18>

  .inputs ResetValue<17>

  .inputs ResetValue<16>

  .inputs ResetValue<15>

  .inputs ResetValue<14>

  .inputs ResetValue<13>

  .inputs ResetValue<12>

  .inputs ResetValue<11>

  .inputs ResetValue<10>

  .inputs ResetValue<9>

  .inputs ResetValue<8>

  .inputs ResetValue<7>

  .inputs ResetValue<6>

  .inputs ResetValue<5>

  .inputs ResetValue<4>

  .inputs ResetValue<3>

  .inputs ResetValue<2>

  .inputs ResetValue<1>

  .inputs ResetValue<0>

  .inputs clk

  .inputs clken

  .inputs enable

  .inputs enable_write

  .inputs si

  .inputs shift

  .inputs update

  .inputs regin<31>

  .inputs regin<30>

  .inputs regin<29>

  .inputs regin<28>

  .inputs regin<27>

  .inputs regin<26>

  .inputs regin<25>

  .inputs regin<24>

  .inputs regin<23>

  .inputs regin<22>

  .inputs regin<21>

  .inputs regin<20>

  .inputs regin<19>

  .inputs regin<18>

  .inputs regin<17>

  .inputs regin<16>

  .inputs regin<15>

  .inputs regin<14>

  .inputs regin<13>

  .inputs regin<12>

  .inputs regin<11>

  .inputs regin<10>

  .inputs regin<9>

  .inputs regin<8>

  .inputs regin<7>

  .inputs regin<6>

  .inputs regin<5>

  .inputs regin<4>

  .inputs regin<3>

  .inputs regin<2>

  .inputs regin<1>

  .inputs regin<0>

  .outputs regout<31>

  .outputs regout<30>

  .outputs regout<29>

  .outputs regout<28>

  .outputs regout<27>

  .outputs regout<26>

  .outputs regout<25>

  .outputs regout<24>

  .outputs regout<23>

  .outputs regout<22>

  .outputs regout<21>

  .outputs regout<20>

  .outputs regout<19>

  .outputs regout<18>

  .outputs regout<17>

  .outputs regout<16>

  .outputs regout<15>

  .outputs regout<14>

  .outputs regout<13>

  .outputs regout<12>

  .outputs regout<11>

  .outputs regout<10>

  .outputs regout<9>

  .outputs regout<8>

  .outputs regout<7>

  .outputs regout<6>

  .outputs regout<5>

  .outputs regout<4>

  .outputs regout<3>

  .outputs regout<2>

  .outputs regout<1>

  .outputs regout<0>

  .outputs so

  .loc Configurable_U5.VHD 603 sh_reg<25>

  .latch n12 sh_reg<25> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<26>

  .latch n11 sh_reg<26> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<27>

  .latch n10 sh_reg<27> re clk 2 n430

  .names enable clken n430

  11 1

  .names shift n5

  0 1

  .names si n5 regin<31> n6

  11- 1

  -01 1

  .names sh_reg<31> n5 regin<30> n7

  11- 1

  -01 1

  .names sh_reg<30> n5 regin<29> n8

  11- 1

  -01 1

  .names sh_reg<29> n5 regin<28> n9

  11- 1

  -01 1

  .names sh_reg<28> n5 regin<27> n10

  11- 1

  -01 1

  .names sh_reg<27> n5 regin<26> n11

  11- 1

  -01 1

  .names sh_reg<26> n5 regin<25> n12

  11- 1

  -01 1

  .names sh_reg<25> n5 regin<24> n13

  11- 1

  -01 1

  .names sh_reg<24> n5 regin<23> n14

  11- 1

  -01 1

  .names sh_reg<23> n5 regin<22> n15

  11- 1

  -01 1

  .names sh_reg<22> n5 regin<21> n16

  11- 1

  -01 1

  .names sh_reg<21> n5 regin<20> n17

  11- 1

  -01 1

  .names sh_reg<20> n5 regin<19> n18

  11- 1

  -01 1

  .names sh_reg<19> n5 regin<18> n19

  11- 1

  -01 1

  .names sh_reg<18> n5 regin<17> n20

  11- 1

  -01 1

  .names sh_reg<17> n5 regin<16> n21

  11- 1

  -01 1

  .names sh_reg<16> n5 regin<15> n22

  11- 1

  -01 1

  .names sh_reg<15> n5 regin<14> n23

  11- 1

  -01 1

  .names sh_reg<14> n5 regin<13> n24

  11- 1

  -01 1

  .names sh_reg<13> n5 regin<12> n25

  11- 1

  -01 1

  .names sh_reg<12> n5 regin<11> n26

  11- 1

  -01 1

  .names sh_reg<11> n5 regin<10> n27

  11- 1

  -01 1

  .names sh_reg<10> n5 regin<9> n28

  11- 1

  -01 1

  .names sh_reg<9> n5 regin<8> n29

  11- 1

  -01 1

  .names sh_reg<8> n5 regin<7> n30

  11- 1

  -01 1

  .names sh_reg<7> n5 regin<6> n31

  11- 1

  -01 1

  .names sh_reg<6> n5 regin<5> n32

  11- 1

  -01 1

  .names sh_reg<5> n5 regin<4> n33

  11- 1

  -01 1

  .names sh_reg<4> n5 regin<3> n34

  11- 1

  -01 1

  .names sh_reg<3> n5 regin<2> n35

  11- 1

  -01 1

  .names sh_reg<2> n5 regin<1> n36

  11- 1

  -01 1

  .names sh_reg<1> n5 regin<0> n37

  11- 1

  -01 1

  .names Rst ResetValue<31> n236

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<30>

  .latch n7 sh_reg<30> re clk 2 n430

  .names update enable n105

  11 1

  .names n105 enable_write n433

  11 1

  .names Rst ResetValue<30> n242

  11 1

  .names Rst ResetValue<29> n246

  11 1

  .names Rst ResetValue<28> n250

  11 1

  .names Rst ResetValue<27> n254

  11 1

  .names Rst ResetValue<26> n258

  11 1

  .names Rst ResetValue<25> n262

  11 1

  .names Rst ResetValue<24> n266

  11 1

  .names Rst ResetValue<23> n270

  11 1

  .names Rst ResetValue<22> n274

  11 1

  .names Rst ResetValue<21> n278

  11 1

  .names Rst ResetValue<20> n282

  11 1

  .names Rst ResetValue<19> n286

  11 1

  .names Rst ResetValue<18> n290

  11 1

  .names Rst ResetValue<17> n294

  11 1

  .names Rst ResetValue<16> n298

  11 1

  .names Rst ResetValue<15> n302

  11 1

  .names Rst ResetValue<14> n306

  11 1

  .names Rst ResetValue<13> n310

  11 1

  .names Rst ResetValue<12> n314

  11 1

  .names Rst ResetValue<11> n318

  11 1

  .names Rst ResetValue<10> n322

  11 1

  .names Rst ResetValue<9> n326

  11 1

  .names Rst ResetValue<8> n330

  11 1

  .names Rst ResetValue<7> n334

  11 1

  .names Rst ResetValue<6> n338

  11 1

  .names Rst ResetValue<5> n342

  11 1

  .names Rst ResetValue<4> n346

  11 1

  .names Rst ResetValue<3> n350

  11 1

  .names Rst ResetValue<2> n354

  11 1

  .names Rst ResetValue<1> n358

  11 1

  .names Rst ResetValue<0> n362

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<24>

  .latch n13 sh_reg<24> re clk 2 n430

  .names up_reg<31> regout<31>

  1 1

  .names up_reg<30> regout<30>

  1 1

  .names up_reg<29> regout<29>

  1 1

  .names up_reg<28> regout<28>

  1 1

  .names up_reg<27> regout<27>

  1 1

  .names up_reg<26> regout<26>

  1 1

  .names up_reg<25> regout<25>

  1 1

  .names up_reg<24> regout<24>

  1 1

  .names up_reg<23> regout<23>

  1 1

  .names up_reg<22> regout<22>

  1 1

  .names up_reg<21> regout<21>

  1 1

  .names up_reg<20> regout<20>

  1 1

  .names up_reg<19> regout<19>

  1 1

  .names up_reg<18> regout<18>

  1 1

  .names up_reg<17> regout<17>

  1 1

  .names up_reg<16> regout<16>

  1 1

  .names up_reg<15> regout<15>

  1 1

  .names up_reg<14> regout<14>

  1 1

  .names up_reg<13> regout<13>

  1 1

  .names up_reg<12> regout<12>

  1 1

  .names up_reg<11> regout<11>

  1 1

  .names up_reg<10> regout<10>

  1 1

  .names up_reg<9> regout<9>

  1 1

  .names up_reg<8> regout<8>

  1 1

  .names up_reg<7> regout<7>

  1 1

  .names up_reg<6> regout<6>

  1 1

  .names up_reg<5> regout<5>

  1 1

  .names up_reg<4> regout<4>

  1 1

  .names up_reg<3> regout<3>

  1 1

  .names up_reg<2> regout<2>

  1 1

  .names up_reg<1> regout<1>

  1 1

  .names up_reg<0> regout<0>

  1 1

  .names sh_reg<0> so

  1 1

  .names ResetValue<31> n237

  0 1

  .names Rst n237 n238

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<28>

  .latch n9 sh_reg<28> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<29>

  .latch n8 sh_reg<29> re clk 2 n430

  .names ResetValue<30> n243

  0 1

  .names Rst n243 n244

  11 1

  .names ResetValue<29> n247

  0 1

  .names Rst n247 n248

  11 1

  .names ResetValue<28> n251

  0 1

  .names Rst n251 n252

  11 1

  .names ResetValue<27> n255

  0 1

  .names Rst n255 n256

  11 1

  .names ResetValue<26> n259

  0 1

  .names Rst n259 n260

  11 1

  .names ResetValue<25> n263

  0 1

  .names Rst n263 n264

  11 1

  .names ResetValue<24> n267

  0 1

  .names Rst n267 n268

  11 1

  .names ResetValue<23> n271

  0 1

  .names Rst n271 n272

  11 1

  .names ResetValue<22> n275

  0 1

  .names Rst n275 n276

  11 1

  .names ResetValue<21> n279

  0 1

  .names Rst n279 n280

  11 1

  .names ResetValue<20> n283

  0 1

  .names Rst n283 n284

  11 1

  .names ResetValue<19> n287

  0 1

  .names Rst n287 n288

  11 1

  .names ResetValue<18> n291

  0 1

  .names Rst n291 n292

  11 1

  .names ResetValue<17> n295

  0 1

  .names Rst n295 n296

  11 1

  .names ResetValue<16> n299

  0 1

  .names Rst n299 n300

  11 1

  .names ResetValue<15> n303

  0 1

  .names Rst n303 n304

  11 1

  .names ResetValue<14> n307

  0 1

  .names Rst n307 n308

  11 1

  .names ResetValue<13> n311

  0 1

  .names Rst n311 n312

  11 1

  .names ResetValue<12> n315

  0 1

  .names Rst n315 n316

  11 1

  .names ResetValue<11> n319

  0 1

  .names Rst n319 n320

  11 1

  .names ResetValue<10> n323

  0 1

  .names Rst n323 n324

  11 1

  .names ResetValue<9> n327

  0 1

  .names Rst n327 n328

  11 1

  .names ResetValue<8> n331

  0 1

  .names Rst n331 n332

  11 1

  .names ResetValue<7> n335

  0 1

  .names Rst n335 n336

  11 1

  .names ResetValue<6> n339

  0 1

  .names Rst n339 n340

  11 1

  .names ResetValue<5> n343

  0 1

  .names Rst n343 n344

  11 1

  .names ResetValue<4> n347

  0 1

  .names Rst n347 n348

  11 1

  .names ResetValue<3> n351

  0 1

  .names Rst n351 n352

  11 1

  .names ResetValue<2> n355

  0 1

  .names Rst n355 n356

  11 1

  .names ResetValue<1> n359

  0 1

  .names Rst n359 n360

  11 1

  .names ResetValue<0> n363

  0 1

  .names Rst n363 n364

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<23>

  .latch n14 sh_reg<23> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<22>

  .latch n15 sh_reg<22> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<21>

  .latch n16 sh_reg<21> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<20>

  .latch n17 sh_reg<20> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<19>

  .latch n18 sh_reg<19> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<18>

  .latch n19 sh_reg<18> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<17>

  .latch n20 sh_reg<17> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<16>

  .latch n21 sh_reg<16> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<15>

  .latch n22 sh_reg<15> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<14>

  .latch n23 sh_reg<14> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<13>

  .latch n24 sh_reg<13> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<12>

  .latch n25 sh_reg<12> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<11>

  .latch n26 sh_reg<11> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<10>

  .latch n27 sh_reg<10> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<9>

  .latch n28 sh_reg<9> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<8>

  .latch n29 sh_reg<8> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<7>

  .latch n30 sh_reg<7> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<6>

  .latch n31 sh_reg<6> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<5>

  .latch n32 sh_reg<5> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<4>

  .latch n33 sh_reg<4> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<3>

  .latch n34 sh_reg<3> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<2>

  .latch n35 sh_reg<2> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<1>

  .latch n36 sh_reg<1> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<0>

  .latch n37 sh_reg<0> re clk 2 n430

  .loc Configurable_U5.VHD 603 sh_reg<31>

  .latch n6 sh_reg<31> re clk 2 n430

  .loc Configurable_U5.VHD 620 up_reg<31>

  .latch sh_reg<31> up_reg<31> re clk 6 n236 n238 n433

  .loc Configurable_U5.VHD 620 up_reg<30>

  .latch sh_reg<30> up_reg<30> re clk 6 n242 n244 n433

  .loc Configurable_U5.VHD 620 up_reg<29>

  .latch sh_reg<29> up_reg<29> re clk 6 n246 n248 n433

  .loc Configurable_U5.VHD 620 up_reg<28>

  .latch sh_reg<28> up_reg<28> re clk 6 n250 n252 n433

  .loc Configurable_U5.VHD 620 up_reg<27>

  .latch sh_reg<27> up_reg<27> re clk 6 n254 n256 n433

  .loc Configurable_U5.VHD 620 up_reg<26>

  .latch sh_reg<26> up_reg<26> re clk 6 n258 n260 n433

  .loc Configurable_U5.VHD 620 up_reg<25>

  .latch sh_reg<25> up_reg<25> re clk 6 n262 n264 n433

  .loc Configurable_U5.VHD 620 up_reg<24>

  .latch sh_reg<24> up_reg<24> re clk 6 n266 n268 n433

  .loc Configurable_U5.VHD 620 up_reg<23>

  .latch sh_reg<23> up_reg<23> re clk 6 n270 n272 n433

  .loc Configurable_U5.VHD 620 up_reg<22>

  .latch sh_reg<22> up_reg<22> re clk 6 n274 n276 n433

  .loc Configurable_U5.VHD 620 up_reg<21>

  .latch sh_reg<21> up_reg<21> re clk 6 n278 n280 n433

  .loc Configurable_U5.VHD 620 up_reg<20>

  .latch sh_reg<20> up_reg<20> re clk 6 n282 n284 n433

  .loc Configurable_U5.VHD 620 up_reg<19>

  .latch sh_reg<19> up_reg<19> re clk 6 n286 n288 n433

  .loc Configurable_U5.VHD 620 up_reg<18>

  .latch sh_reg<18> up_reg<18> re clk 6 n290 n292 n433

  .loc Configurable_U5.VHD 620 up_reg<17>

  .latch sh_reg<17> up_reg<17> re clk 6 n294 n296 n433

  .loc Configurable_U5.VHD 620 up_reg<16>

  .latch sh_reg<16> up_reg<16> re clk 6 n298 n300 n433

  .loc Configurable_U5.VHD 620 up_reg<15>

  .latch sh_reg<15> up_reg<15> re clk 6 n302 n304 n433

  .loc Configurable_U5.VHD 620 up_reg<14>

  .latch sh_reg<14> up_reg<14> re clk 6 n306 n308 n433

  .loc Configurable_U5.VHD 620 up_reg<13>

  .latch sh_reg<13> up_reg<13> re clk 6 n310 n312 n433

  .loc Configurable_U5.VHD 620 up_reg<12>

  .latch sh_reg<12> up_reg<12> re clk 6 n314 n316 n433

  .loc Configurable_U5.VHD 620 up_reg<11>

  .latch sh_reg<11> up_reg<11> re clk 6 n318 n320 n433

  .loc Configurable_U5.VHD 620 up_reg<10>

  .latch sh_reg<10> up_reg<10> re clk 6 n322 n324 n433

  .loc Configurable_U5.VHD 620 up_reg<9>

  .latch sh_reg<9> up_reg<9> re clk 6 n326 n328 n433

  .loc Configurable_U5.VHD 620 up_reg<8>

  .latch sh_reg<8> up_reg<8> re clk 6 n330 n332 n433

  .loc Configurable_U5.VHD 620 up_reg<7>

  .latch sh_reg<7> up_reg<7> re clk 6 n334 n336 n433

  .loc Configurable_U5.VHD 620 up_reg<6>

  .latch sh_reg<6> up_reg<6> re clk 6 n338 n340 n433

  .loc Configurable_U5.VHD 620 up_reg<5>

  .latch sh_reg<5> up_reg<5> re clk 6 n342 n344 n433

  .loc Configurable_U5.VHD 620 up_reg<4>

  .latch sh_reg<4> up_reg<4> re clk 6 n346 n348 n433

  .loc Configurable_U5.VHD 620 up_reg<3>

  .latch sh_reg<3> up_reg<3> re clk 6 n350 n352 n433

  .loc Configurable_U5.VHD 620 up_reg<2>

  .latch sh_reg<2> up_reg<2> re clk 6 n354 n356 n433

  .loc Configurable_U5.VHD 620 up_reg<1>

  .latch sh_reg<1> up_reg<1> re clk 6 n358 n360 n433

  .loc Configurable_U5.VHD 620 up_reg<0>

  .latch sh_reg<0> up_reg<0> re clk 6 n362 n364 n433