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fpga/FPGA_projet/ProjectOutputs/Default - All Constraints/_blf/cell0007_body.blf 714 Bytes
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  .model Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_1_

  .inputs Rst

  .inputs ResetValue<0>

  .inputs clk

  .inputs clken

  .inputs enable

  .inputs enable_write

  .inputs si

  .inputs shift

  .inputs update

  .inputs regin<0>

  .outputs regout<0>

  .outputs so

  .names enable clken n4

  11 1

  .names regin<0> shift si n6

  11- 1

  -01 1

  .names Rst ResetValue<0> n19

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<0>

  .latch n6 sh_reg<0> re clk 2 n4

  .names update enable n12

  11 1

  .names n12 enable_write n13

  11 1

  .names up_reg<0> regout<0>

  1 1

  .names sh_reg<0> so

  1 1

  .names ResetValue<0> n20

  0 1

  .names Rst n20 n21

  11 1

  .loc Configurable_U5.VHD 620 up_reg<0>

  .latch sh_reg<0> up_reg<0> re clk 6 n19 n21 n13