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fpga/FPGA_projet/ProjectOutputs/Default - All Constraints/_blf/cell0005_body.blf 3.46 KB
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  .model Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR_8_

  .inputs Rst

  .inputs ResetValue<7>

  .inputs ResetValue<6>

  .inputs ResetValue<5>

  .inputs ResetValue<4>

  .inputs ResetValue<3>

  .inputs ResetValue<2>

  .inputs ResetValue<1>

  .inputs ResetValue<0>

  .inputs clk

  .inputs clken

  .inputs enable

  .inputs enable_write

  .inputs si

  .inputs shift

  .inputs update

  .inputs regin<7>

  .inputs regin<6>

  .inputs regin<5>

  .inputs regin<4>

  .inputs regin<3>

  .inputs regin<2>

  .inputs regin<1>

  .inputs regin<0>

  .outputs regout<7>

  .outputs regout<6>

  .outputs regout<5>

  .outputs regout<4>

  .outputs regout<3>

  .outputs regout<2>

  .outputs regout<1>

  .outputs regout<0>

  .outputs so

  .loc Configurable_U5.VHD 603 sh_reg<1>

  .latch n12 sh_reg<1> re clk 2 n118

  .loc Configurable_U5.VHD 603 sh_reg<2>

  .latch n11 sh_reg<2> re clk 2 n118

  .loc Configurable_U5.VHD 603 sh_reg<3>

  .latch n10 sh_reg<3> re clk 2 n118

  .names enable clken n118

  11 1

  .names shift n5

  0 1

  .names si n5 regin<7> n6

  11- 1

  -01 1

  .names sh_reg<7> n5 regin<6> n7

  11- 1

  -01 1

  .names sh_reg<6> n5 regin<5> n8

  11- 1

  -01 1

  .names sh_reg<5> n5 regin<4> n9

  11- 1

  -01 1

  .names sh_reg<4> n5 regin<3> n10

  11- 1

  -01 1

  .names sh_reg<3> n5 regin<2> n11

  11- 1

  -01 1

  .names sh_reg<2> n5 regin<1> n12

  11- 1

  -01 1

  .names sh_reg<1> n5 regin<0> n13

  11- 1

  -01 1

  .names Rst ResetValue<7> n68

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<6>

  .latch n7 sh_reg<6> re clk 2 n118

  .names update enable n33

  11 1

  .names n33 enable_write n121

  11 1

  .names Rst ResetValue<6> n74

  11 1

  .names Rst ResetValue<5> n78

  11 1

  .names Rst ResetValue<4> n82

  11 1

  .names Rst ResetValue<3> n86

  11 1

  .names Rst ResetValue<2> n90

  11 1

  .names Rst ResetValue<1> n94

  11 1

  .names Rst ResetValue<0> n98

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<0>

  .latch n13 sh_reg<0> re clk 2 n118

  .names up_reg<7> regout<7>

  1 1

  .names up_reg<6> regout<6>

  1 1

  .names up_reg<5> regout<5>

  1 1

  .names up_reg<4> regout<4>

  1 1

  .names up_reg<3> regout<3>

  1 1

  .names up_reg<2> regout<2>

  1 1

  .names up_reg<1> regout<1>

  1 1

  .names up_reg<0> regout<0>

  1 1

  .names sh_reg<0> so

  1 1

  .names ResetValue<7> n69

  0 1

  .names Rst n69 n70

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<4>

  .latch n9 sh_reg<4> re clk 2 n118

  .loc Configurable_U5.VHD 603 sh_reg<5>

  .latch n8 sh_reg<5> re clk 2 n118

  .names ResetValue<6> n75

  0 1

  .names Rst n75 n76

  11 1

  .names ResetValue<5> n79

  0 1

  .names Rst n79 n80

  11 1

  .names ResetValue<4> n83

  0 1

  .names Rst n83 n84

  11 1

  .names ResetValue<3> n87

  0 1

  .names Rst n87 n88

  11 1

  .names ResetValue<2> n91

  0 1

  .names Rst n91 n92

  11 1

  .names ResetValue<1> n95

  0 1

  .names Rst n95 n96

  11 1

  .names ResetValue<0> n99

  0 1

  .names Rst n99 n100

  11 1

  .loc Configurable_U5.VHD 603 sh_reg<7>

  .latch n6 sh_reg<7> re clk 2 n118

  .loc Configurable_U5.VHD 620 up_reg<7>

  .latch sh_reg<7> up_reg<7> re clk 6 n68 n70 n121

  .loc Configurable_U5.VHD 620 up_reg<6>

  .latch sh_reg<6> up_reg<6> re clk 6 n74 n76 n121

  .loc Configurable_U5.VHD 620 up_reg<5>

  .latch sh_reg<5> up_reg<5> re clk 6 n78 n80 n121

  .loc Configurable_U5.VHD 620 up_reg<4>

  .latch sh_reg<4> up_reg<4> re clk 6 n82 n84 n121

  .loc Configurable_U5.VHD 620 up_reg<3>

  .latch sh_reg<3> up_reg<3> re clk 6 n86 n88 n121

  .loc Configurable_U5.VHD 620 up_reg<2>

  .latch sh_reg<2> up_reg<2> re clk 6 n90 n92 n121

  .loc Configurable_U5.VHD 620 up_reg<1>

  .latch sh_reg<1> up_reg<1> re clk 6 n94 n96 n121

  .loc Configurable_U5.VHD 620 up_reg<0>

  .latch sh_reg<0> up_reg<0> re clk 6 n98 n100 n121