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fpga/FPGA_projet/ProjectOutputs/Default - All Constraints/FPGA_projet.synthlog 8.5 KB
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  ###############################################################################

  ### Altium HDL Synthesizer 1.1.0.1

  ### Copyright (C) 2005-2009, Altium Limited. All Rights Reserved

  ###############################################################################

  ### Timestamp: 5/17/2017 6:18:52 PM

  ###############################################################################

  ### Commandline: AltiumSynthesizer.exe "-o" "FPGA_projet.mof" "-p" "FPGA_projet.mpf"

  ###

  ### Options:

  ###

  ### Synthesizing FPGA_projet for Spartan3

  ### Entity                  : FPGA_projet

  ### VerilogMode             : 1 (0=Verilog95, 1=Verilog2001, 2=VerilogSystem, 3=Ams)

  ### VHDL87                  : False

  ### Insert Toplevel Buffers : True

  ### Combinational Logic Opt : 3 (1=Low, 3=Normal, 5=High)

  ###############################################################################

  ### Compilation Report

  ###############################################################################

  

  ##N|The default vhdl library search path is now "C:/Users/Public/Documents/Altium/AD16/Library/VHDL/VHDL93"

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\Configurable_U1.VHD

  Restoring VHDL parse-tree ieee.std_logic_1164 from C:/Users/Public/Documents/Altium/AD16/Library/VHDL/VHDL93/ieee/std_logic_1164.vdb

  Restoring VHDL parse-tree std.standard from C:/Users/Public/Documents/Altium/AD16/Library/VHDL/VHDL93/std/standard.vdb

  Restoring VHDL parse-tree ieee.std_logic_unsigned from C:/Users/Public/Documents/Altium/AD16/Library/VHDL/VHDL93/ieee/std_logic_unsigned.vdb

  Restoring VHDL parse-tree ieee.std_logic_arith from C:/Users/Public/Documents/Altium/AD16/Library/VHDL/VHDL93/ieee/std_logic_arith.vdb

  ##N|Configurable_U1.VHD|8|analyzing entity configurable_u1

  ##N|Configurable_U1.VHD|18|analyzing architecture structure

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\Configurable_U2.VHD

  ##N|Configurable_U2.VHD|7|analyzing entity configurable_u2

  ##N|Configurable_U2.VHD|17|analyzing architecture structure

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\Configurable_U4.VHD

  ##N|Configurable_U4.VHD|8|analyzing entity configurable_u4

  ##N|Configurable_U4.VHD|18|analyzing architecture structure

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\Configurable_U5.VHD

  ##N|Configurable_U5.VHD|6|analyzing package configurable_u5tap_utils

  ##N|Configurable_U5.VHD|71|analyzing package body configurable_u5tap_utils

  ##N|Configurable_U5.VHD|82|analyzing entity configurable_u5universal_digital_io_drnoout

  ##N|Configurable_U5.VHD|98|analyzing architecture rtl

  ##N|Configurable_U5.VHD|134|analyzing entity configurable_u5universal_digital_io_tapcontroller

  ##N|Configurable_U5.VHD|168|analyzing architecture rtl

  ##N|Configurable_U5.VHD|558|analyzing entity configurable_u5universal_digital_io_datareg_inout_wr

  ##N|Configurable_U5.VHD|580|analyzing architecture rtl

  ##N|Configurable_U5.VHD|640|analyzing entity configurable_u5

  ##N|Configurable_U5.VHD|657|analyzing architecture rtl

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\Configurable_U6.VHD

  ##N|Configurable_U6.VHD|7|analyzing entity configurable_u6

  ##N|Configurable_U6.VHD|23|analyzing architecture structure

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\reception.Vhd

  ##N|reception.Vhd|10|analyzing entity reception_rs232

  ##N|reception.Vhd|19|analyzing architecture behavioral

  Analyzing VHDL file C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\essai1.VHD

  ##N|essai1.VHD|16|analyzing entity fpga_projet

  ##N|essai1.VHD|55|analyzing architecture structure

  ###############################################################################

  ### Elaboration Report

  ###############################################################################

  

  executing Configurable_U1(structure)

  ##I|syn_arit.vhd|1623|-- found LessThan: 8<8

  ##I|syn_arit.vhd|1697|-- found LessThan: 8<8

  ##I|Configurable_U1.VHD|37|-- found Adder: 8+8

  executing Configurable_U2(structure)

  executing Configurable_U4(structure)

  ##I|Configurable_U4.VHD|28|-- found LessThan: 8<8

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DRNOOUT(RTL)

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_TAPCONTROLLER(rtl)

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DRNOOUT(32)(RTL)

  ##N|Configurable_U5.VHD|278|others clause is never selected

  ##I|Configurable_U5.VHD|279|-- possible Multiplexer: 16-1 for tapstate_nxt

  ##N|Configurable_U5.VHD|298|others clause is never selected

  ##I|Configurable_U5.VHD|299|-- possible Multiplexer: 16-1 for tapstate_nxt

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR(RTL)

  executing Configurable_U5(RTL)

  ##W|Configurable_U5.VHD|747|using initial value "U" for registerinput_value_signal since it is never assigned

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR(8)(RTL)

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR(16)(RTL)

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR(1)(RTL)

  executing Configurable_U5UNIVERSAL_DIGITAL_IO_DATAREG_INOUT_WR(32)(RTL)

  ##I|Configurable_U5.VHD|932|-- found Adder: 4+4

  executing Configurable_U6(structure)

  executing reception_RS232(Behavioral)

  ##I|reception.Vhd|60|-- found Adder: 4+4

  ##I|reception.Vhd|79|-- found Adder: 32+32

  executing FPGA_projet(Structure)

  

  ###############################################################################

  ### Synthesis Report

  ###############################################################################

  

  ##O|essai1.VHD|191|Dissolving instance U6(Configurable_U6)

  ##O|essai1.VHD|216|Dissolving instance U4(Configurable_U4)

  ###############################################################################

  ### Optimization Report

  ###  command: mmHDLtoEDIF -f xilinx -n spartan3 -p spartan3 -z 3 -o "C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet.edf" -b "C:\Users\Altium7\Documents\csaadVandamme\FPGA_projet\ProjectOutputs\Default - All Constraints\FPGA_projet.bfl" -e FPGA_projet -L "C:\Users\Public\Documents\Altium\AD16\Library/" 

  

  INFO LibDir:  "C:\Users\Public\Documents\Altium\AD16\Library/"
  

  INFO ConstraintsMap:  "C:\Users\Public\Documents\Altium\AD16\Library/vhdl_lib/VendorConstraints.map"
  

  optimizing "_blf/cell0001"

  optimizing "_blf/cell0002"

  optimizing "_blf/cell0003"

  optimizing "_blf/cell0004"

  optimizing "_blf/cell0005"

  optimizing "_blf/cell0006"

  optimizing "_blf/cell0007"

  optimizing "_blf/cell0008"

  optimizing "_blf/cell0009"

  optimizing "_blf/cell0010"

   

  ###############################################################################

  ### Design Statistics

  ###############################################################################

   

  Flipflops:                                                 : 232

      Flipflops with RESET                    (Synchronous)  : 8

      Flipflops with RESET                    (Asynchronous) : 3

      Flipflops with PRESET                   (Asynchronous) : 4

      Flipflops                                              : 9

      Flipflops with RESET and ENABLE         (Synchronous)  : 7

      Flipflops with PRESET and ENABLE        (Asynchronous) : 2

      Flipflops with PRESET, RESET and ENABLE (Asynchronous) : 81

      Flipflops with ENABLE                                  : 118

                                                             

  MacroCells:                                                

      CD4CES                                                 : 2

      CLKGEN                                                 : 1

      MUXCY                                                  : 24

      XORCY                                                  : 10

      MUXF5                                                  : 4

      MUXF6                                                  : 2

                                                             

  Area Estimates:                                            

      Area Estimate (2 Input Gate Count)                     : 519

      Area Estimate (LUT Count)                              : 358

   

  ###############################################################################

   

  formating EDIF....                            

  

  ###############################################################################

  Synthesis successful

  ###############################################################################