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LIBRARY IEEE;
USE IEEE.Std_Logic_1164.all;
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ENTITY Configurable_U2 IS
PORT(
D_B : IN std_logic_vector(7 downto 0):=(OTHERS => 'U');
Q_B : OUT std_logic_vector(7 downto 0) := (Others=>'0');
C : IN std_logic:='U'
);
END Configurable_U2;
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ARCHITECTURE structure OF Configurable_U2 IS
BEGIN
PROCESS(C)
BEGIN
IF ( C'Event and C = '1' ) THEN
Q_B <= D_B;
END IF;
END PROCESS;
END structure;
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