/**
    ******************************************************************************
    * @file    stm32f4xx_hal_dma.h
    * @author  MCD Application Team
    * @version V1.4.1
    * @date    09-October-2015
    * @brief   Header file of DMA HAL module.
    ******************************************************************************
    * @attention
    *
    * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
    *
    * Redistribution and use in source and binary forms, with or without modification,
    * are permitted provided that the following conditions are met:
    *   1. Redistributions of source code must retain the above copyright notice,
    *      this list of conditions and the following disclaimer.
    *   2. Redistributions in binary form must reproduce the above copyright notice,
    *      this list of conditions and the following disclaimer in the documentation
    *      and/or other materials provided with the distribution.
    *   3. Neither the name of STMicroelectronics nor the names of its contributors
    *      may be used to endorse or promote products derived from this software
    *      without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
    * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
    * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
    * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
    * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    ******************************************************************************
    */ 
  
  /* Define to prevent recursive inclusion -------------------------------------*/
  #ifndef __STM32F4xx_HAL_DMA_H
  #define __STM32F4xx_HAL_DMA_H
  
  #ifdef __cplusplus
   extern "C" {
  #endif
  
  /* Includes ------------------------------------------------------------------*/
  #include "stm32f4xx_hal_def.h"
  
  /** @addtogroup STM32F4xx_HAL_Driver
    * @{
    */
  
  /** @addtogroup DMA
    * @{
    */ 
  
  /* Exported types ------------------------------------------------------------*/
  
  /** @defgroup DMA_Exported_Types DMA Exported Types
    * @brief    DMA Exported Types 
    * @{
    */
     
  /** 
    * @brief  DMA Configuration Structure definition
    */
  typedef struct
  {
    uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
                                        This parameter can be a value of @ref DMA_Channel_selection                    */
  
    uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
                                        from memory to memory or from peripheral to memory.
                                        This parameter can be a value of @ref DMA_Data_transfer_direction              */
  
    uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
                                        This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
  
    uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
                                        This parameter can be a value of @ref DMA_Memory_incremented_mode              */
  
    uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
                                        This parameter can be a value of @ref DMA_Peripheral_data_size                 */
  
    uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
                                        This parameter can be a value of @ref DMA_Memory_data_size                     */
  
    uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
                                        This parameter can be a value of @ref DMA_mode
                                        @note The circular buffer mode cannot be used if the memory-to-memory
                                              data transfer is configured on the selected Stream                        */
  
    uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
                                        This parameter can be a value of @ref DMA_Priority_level                       */
  
    uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
                                        This parameter can be a value of @ref DMA_FIFO_direct_mode
                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
                                              memory-to-memory data transfer is configured on the selected stream       */
  
    uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
                                        This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
  
    uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
                                        It specifies the amount of data to be transferred in a single non interruptible
                                        transaction.
                                        This parameter can be a value of @ref DMA_Memory_burst 
                                        @note The burst mode is possible only if the address Increment mode is enabled. */
  
    uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
                                        It specifies the amount of data to be transferred in a single non interruptable 
                                        transaction. 
                                        This parameter can be a value of @ref DMA_Peripheral_burst
                                        @note The burst mode is possible only if the address Increment mode is enabled. */
  }DMA_InitTypeDef;
  
  
  /** 
    * @brief  HAL DMA State structures definition
    */
  typedef enum
  {
    HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
    HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
    HAL_DMA_STATE_READY_MEM0        = 0x11,  /*!< DMA Mem0 process success            */
    HAL_DMA_STATE_READY_MEM1        = 0x21,  /*!< DMA Mem1 process success            */
    HAL_DMA_STATE_READY_HALF_MEM0   = 0x31,  /*!< DMA Mem0 Half process success       */
    HAL_DMA_STATE_READY_HALF_MEM1   = 0x41,  /*!< DMA Mem1 Half process success       */
    HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
    HAL_DMA_STATE_BUSY_MEM0         = 0x12,  /*!< DMA Mem0 process is ongoing         */
    HAL_DMA_STATE_BUSY_MEM1         = 0x22,  /*!< DMA Mem1 process is ongoing         */
    HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
    HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
  }HAL_DMA_StateTypeDef;
  
  /** 
    * @brief  HAL DMA Error Code structure definition
    */
  typedef enum
  {
    HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
    HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
  }HAL_DMA_LevelCompleteTypeDef;
  
  /** 
    * @brief  DMA handle Structure definition
    */
  typedef struct __DMA_HandleTypeDef
  {
    DMA_Stream_TypeDef         *Instance;                                                    /*!< Register base address                  */
  
    DMA_InitTypeDef            Init;                                                         /*!< DMA communication parameters           */ 
  
    HAL_LockTypeDef            Lock;                                                         /*!< DMA locking object                     */  
  
    __IO HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
  
    void                       *Parent;                                                      /*!< Parent object state                    */  
  
    void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
  
    void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
  
    void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer complete Memory1 callback */
  
    void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
  
   __IO uint32_t               ErrorCode;                                                    /*!< DMA Error code                         */
  
   uint32_t                    StreamBaseAddress;                                            /*!< DMA Stream Base Address                */
  
   uint32_t                    StreamIndex;                                                  /*!< DMA Stream Index                       */ 
  }DMA_HandleTypeDef;
  
  /**
    * @}
    */
  
  /* Exported constants --------------------------------------------------------*/
  
  /** @defgroup DMA_Exported_Constants DMA Exported Constants
    * @brief    DMA Exported constants 
    * @{
    */
  
  /** @defgroup DMA_Error_Code DMA Error Code
    * @brief    DMA Error Code 
    * @{
    */ 
  #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
  #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
  #define HAL_DMA_ERROR_FE        ((uint32_t)0x00000002)    /*!< FIFO error           */
  #define HAL_DMA_ERROR_DME       ((uint32_t)0x00000004)    /*!< Direct Mode error    */
  #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
  /**
    * @}
    */
  
  /** @defgroup DMA_Channel_selection DMA Channel selection
    * @brief    DMA channel selection 
    * @{
    */ 
  #define DMA_CHANNEL_0        ((uint32_t)0x00000000)  /*!< DMA Channel 0 */
  #define DMA_CHANNEL_1        ((uint32_t)0x02000000)  /*!< DMA Channel 1 */
  #define DMA_CHANNEL_2        ((uint32_t)0x04000000)  /*!< DMA Channel 2 */
  #define DMA_CHANNEL_3        ((uint32_t)0x06000000)  /*!< DMA Channel 3 */
  #define DMA_CHANNEL_4        ((uint32_t)0x08000000)  /*!< DMA Channel 4 */
  #define DMA_CHANNEL_5        ((uint32_t)0x0A000000)  /*!< DMA Channel 5 */
  #define DMA_CHANNEL_6        ((uint32_t)0x0C000000)  /*!< DMA Channel 6 */
  #define DMA_CHANNEL_7        ((uint32_t)0x0E000000)  /*!< DMA Channel 7 */
  /**
    * @}
    */
  
  /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
    * @brief    DMA data transfer direction 
    * @{
    */ 
  #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
  #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
  #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
  /**
    * @}
    */  
          
  /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
    * @brief    DMA peripheral incremented mode 
    * @{
    */ 
  #define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */
  #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode disable */
  /**
    * @}
    */ 
  
  /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
    * @brief    DMA memory incremented mode 
    * @{
    */ 
  #define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */
  #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode disable */
  /**
    * @}
    */
  
  /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
    * @brief    DMA peripheral data size 
    * @{
    */ 
  #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
  #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord */
  #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word     */
  /**
    * @}
    */ 
  
  /** @defgroup DMA_Memory_data_size DMA Memory data size
    * @brief    DMA memory data size 
    * @{ 
    */
  #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
  #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */
  #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */
  /**
    * @}
    */
  
  /** @defgroup DMA_mode DMA mode
    * @brief    DMA mode 
    * @{
    */ 
  #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
  #define DMA_CIRCULAR       ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
  #define DMA_PFCTRL         ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
  /**
    * @}
    */
  
  /** @defgroup DMA_Priority_level DMA Priority level
    * @brief    DMA priority levels 
    * @{
    */
  #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level: Low       */
  #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */
  #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */
  #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */
  /**
    * @}
    */ 
  
  /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
    * @brief    DMA FIFO direct mode
    * @{
    */
  #define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000)       /*!< FIFO mode disable */
  #define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */
  /**
    * @}
    */ 
  
  /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
    * @brief    DMA FIFO level 
    * @{
    */
  #define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000)       /*!< FIFO threshold 1 quart full configuration  */
  #define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
  #define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
  #define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
  /**
    * @}
    */ 
  
  /** @defgroup DMA_Memory_burst DMA Memory burst
    * @brief    DMA memory burst 
    * @{
    */ 
  #define DMA_MBURST_SINGLE       ((uint32_t)0x00000000)  
  #define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)  
  #define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)  
  #define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)  
  /**
    * @}
    */ 
  
  /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
    * @brief    DMA peripheral burst 
    * @{
    */ 
  #define DMA_PBURST_SINGLE       ((uint32_t)0x00000000)  
  #define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)  
  #define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)  
  #define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)  
  /**
    * @}
    */
  
  /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
    * @brief    DMA interrupts definition 
    * @{
    */
  #define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)
  #define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)
  #define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)
  #define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)
  #define DMA_IT_FE                         ((uint32_t)0x00000080)
  /**
    * @}
    */
  
  /** @defgroup DMA_flag_definitions DMA flag definitions
    * @brief    DMA flag definitions 
    * @{
    */ 
  #define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00800001)
  #define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00800004)
  #define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008)
  #define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010)
  #define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020)
  #define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040)
  #define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100)
  #define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200)
  #define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400)
  #define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800)
  #define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000)
  #define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000)
  #define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000)
  #define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000)
  #define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000)
  #define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000)
  #define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000)
  #define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000)
  #define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000)
  #define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000)
  /**
    * @}
    */
  
  /**
    * @}
    */
   
  /* Exported macro ------------------------------------------------------------*/
  
  /** @brief Reset DMA handle state
    * @param  __HANDLE__: specifies the DMA handle.
    * @retval None
    */
  #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
  
  /**
    * @brief  Return the current DMA Stream FIFO filled level.
    * @param  __HANDLE__: DMA handle
    * @retval The FIFO filling state.
    *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
    *                                              and not empty.
    *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
    *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
    *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
    *           - DMA_FIFOStatus_Empty: when FIFO is empty
    *           - DMA_FIFOStatus_Full: when FIFO is full
    */
  #define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
  
  /**
    * @brief  Enable the specified DMA Stream.
    * @param  __HANDLE__: DMA handle
    * @retval None
    */
  #define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
  
  /**
    * @brief  Disable the specified DMA Stream.
    * @param  __HANDLE__: DMA handle
    * @retval None
    */
  #define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
  
  /* Interrupt & Flag management */
  
  /**
    * @brief  Return the current DMA Stream transfer complete flag.
    * @param  __HANDLE__: DMA handle
    * @retval The specified transfer complete flag index.
    */
  #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
     DMA_FLAG_TCIF3_7)
  
  /**
    * @brief  Return the current DMA Stream half transfer complete flag.
    * @param  __HANDLE__: DMA handle
    * @retval The specified half transfer complete flag index.
    */      
  #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
     DMA_FLAG_HTIF3_7)
  
  /**
    * @brief  Return the current DMA Stream transfer error flag.
    * @param  __HANDLE__: DMA handle
    * @retval The specified transfer error flag index.
    */
  #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
     DMA_FLAG_TEIF3_7)
  
  /**
    * @brief  Return the current DMA Stream FIFO error flag.
    * @param  __HANDLE__: DMA handle
    * @retval The specified FIFO error flag index.
    */
  #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
     DMA_FLAG_FEIF3_7)
  
  /**
    * @brief  Return the current DMA Stream direct mode error flag.
    * @param  __HANDLE__: DMA handle
    * @retval The specified direct mode error flag index.
    */
  #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
  (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
   ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
     DMA_FLAG_DMEIF3_7)
  
  /**
    * @brief  Get the DMA Stream pending flags.
    * @param  __HANDLE__: DMA handle
    * @param  __FLAG__: Get the specified flag.
    *          This parameter can be any combination of the following values:
    *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
    *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
    *            @arg DMA_FLAG_TEIFx: Transfer error flag.
    *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
    *            @arg DMA_FLAG_FEIFx: FIFO error flag.
    *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
    * @retval The state of FLAG (SET or RESET).
    */
  #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
  (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
   ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
   ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
  
  /**
    * @brief  Clear the DMA Stream pending flags.
    * @param  __HANDLE__: DMA handle
    * @param  __FLAG__: specifies the flag to clear.
    *          This parameter can be any combination of the following values:
    *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
    *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
    *            @arg DMA_FLAG_TEIFx: Transfer error flag.
    *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
    *            @arg DMA_FLAG_FEIFx: FIFO error flag.
    *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
    * @retval None
    */
  #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
  (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
   ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
   ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
  
  /**
    * @brief  Enable the specified DMA Stream interrupts.
    * @param  __HANDLE__: DMA handle
    * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
    *        This parameter can be any combination of the following values:
    *           @arg DMA_IT_TC: Transfer complete interrupt mask.
    *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
    *           @arg DMA_IT_TE: Transfer error interrupt mask.
    *           @arg DMA_IT_FE: FIFO error interrupt mask.
    *           @arg DMA_IT_DME: Direct mode error interrupt.
    * @retval None
    */
  #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
  
  /**
    * @brief  Disable the specified DMA Stream interrupts.
    * @param  __HANDLE__: DMA handle
    * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
    *         This parameter can be any combination of the following values:
    *            @arg DMA_IT_TC: Transfer complete interrupt mask.
    *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
    *            @arg DMA_IT_TE: Transfer error interrupt mask.
    *            @arg DMA_IT_FE: FIFO error interrupt mask.
    *            @arg DMA_IT_DME: Direct mode error interrupt.
    * @retval None
    */
  #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
  
  /**
    * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
    * @param  __HANDLE__: DMA handle
    * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
    *         This parameter can be one of the following values:
    *            @arg DMA_IT_TC: Transfer complete interrupt mask.
    *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
    *            @arg DMA_IT_TE: Transfer error interrupt mask.
    *            @arg DMA_IT_FE: FIFO error interrupt mask.
    *            @arg DMA_IT_DME: Direct mode error interrupt.
    * @retval The state of DMA_IT.
    */
  #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
                                                          ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
                                                          ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
  
  /**
    * @brief  Writes the number of data units to be transferred on the DMA Stream.
    * @param  __HANDLE__: DMA handle
    * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535) 
    *          Number of data items depends only on the Peripheral data format.
    *            
    * @note   If Peripheral data format is Bytes: number of data units is equal 
    *         to total number of bytes to be transferred.
    *           
    * @note   If Peripheral data format is Half-Word: number of data units is  
    *         equal to total number of bytes to be transferred / 2.
    *           
    * @note   If Peripheral data format is Word: number of data units is equal 
    *         to total  number of bytes to be transferred / 4.
    *      
    * @retval The number of remaining data units in the current DMAy Streamx transfer.
    */
  #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
  
  /**
    * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
    * @param  __HANDLE__: DMA handle
    *   
    * @retval The number of remaining data units in the current DMA Stream transfer.
    */
  #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
  
  
  /* Include DMA HAL Extension module */
  #include "stm32f4xx_hal_dma_ex.h"   
  
  /* Exported functions --------------------------------------------------------*/
  
  /** @defgroup DMA_Exported_Functions DMA Exported Functions
    * @brief    DMA Exported functions 
    * @{
    */
  
  /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
    * @brief   Initialization and de-initialization functions 
    * @{
    */
  HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
  HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
  /**
    * @}
    */
  
  /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
    * @brief   I/O operation functions  
    * @{
    */
  HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
  HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
  HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
  void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
  /**
    * @}
    */ 
  
  /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
    * @brief    Peripheral State functions 
    * @{
    */
  HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
  uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
  /**
    * @}
    */ 
  /**
    * @}
    */ 
  /* Private Constants -------------------------------------------------------------*/
  /** @defgroup DMA_Private_Constants DMA Private Constants
    * @brief    DMA private defines and constants 
    * @{
    */
  /**
    * @}
    */ 
  
  /* Private macros ------------------------------------------------------------*/
  /** @defgroup DMA_Private_Macros DMA Private Macros
    * @brief    DMA private macros 
    * @{
    */
  #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
                                   ((CHANNEL) == DMA_CHANNEL_1) || \
                                   ((CHANNEL) == DMA_CHANNEL_2) || \
                                   ((CHANNEL) == DMA_CHANNEL_3) || \
                                   ((CHANNEL) == DMA_CHANNEL_4) || \
                                   ((CHANNEL) == DMA_CHANNEL_5) || \
                                   ((CHANNEL) == DMA_CHANNEL_6) || \
                                   ((CHANNEL) == DMA_CHANNEL_7))
  
  #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                       ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
                                       ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
  
  #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
  
  #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
                                              ((STATE) == DMA_PINC_DISABLE))
  
  #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
                                          ((STATE) == DMA_MINC_DISABLE))
  
  #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
                                             ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
                                             ((SIZE) == DMA_PDATAALIGN_WORD))
  
  #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
                                         ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
                                         ((SIZE) == DMA_MDATAALIGN_WORD ))
  
  #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
                             ((MODE) == DMA_CIRCULAR) || \
                             ((MODE) == DMA_PFCTRL)) 
  
  #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
                                     ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
                                     ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
                                     ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
  
  #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
                                         ((STATE) == DMA_FIFOMODE_ENABLE))
  
  #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
                                            ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
                                            ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
                                            ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
  
  #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
                                      ((BURST) == DMA_MBURST_INC4)   || \
                                      ((BURST) == DMA_MBURST_INC8)   || \
                                      ((BURST) == DMA_MBURST_INC16))
  
  #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
                                          ((BURST) == DMA_PBURST_INC4)   || \
                                          ((BURST) == DMA_PBURST_INC8)   || \
                                          ((BURST) == DMA_PBURST_INC16))
  /**
    * @}
    */ 
  
  /* Private functions ---------------------------------------------------------*/
  /** @defgroup DMA_Private_Functions DMA Private Functions
    * @brief    DMA private  functions 
    * @{
    */
  /**
    * @}
    */
  
  /**
    * @}
    */ 
  
  /**
    * @}
    */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* __STM32F4xx_HAL_DMA_H */
  
  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/