From 2962f7e6fdcce5076358a15154c09bc8b905dda5 Mon Sep 17 00:00:00 2001 From: Geoffrey Frogeye Date: Thu, 11 May 2017 06:55:57 +0200 Subject: [PATCH] Outils pour compiler un programme --- .gitignore | 1 + Makefile | 6 ++++++ chen.txt | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ configure | 8 +++++++- scripts/.gitignore | 1 + scripts/Compilateur.exe | Bin 0 -> 532992 bytes scripts/gram.txt | 791 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 868 insertions(+), 1 deletion(-) create mode 100644 chen.txt create mode 100644 scripts/.gitignore create mode 100644 scripts/Compilateur.exe create mode 100644 scripts/gram.txt diff --git a/.gitignore b/.gitignore index 433fe87..31da110 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,4 @@ !template.html *.lst *.err +*.hex diff --git a/Makefile b/Makefile index d868f22..63f1580 100644 --- a/Makefile +++ b/Makefile @@ -18,14 +18,20 @@ SOURCES=$(wildcard *.asm) $(wildcard *.txt) # PROGRAMME +%.asm: %.txt + wine scripts/Compilateur.exe scripts/gram.txt "$<" "$@" + %.hex: %.asm scripts/gavrasm "$<" %.upload: %.hex avrdude -C scripts/avrdude.conf -v -p atmega2560 -c wiring -P /dev/ttyACM0 -b 115200 -D -U flash:w:"$<":i +%.up: %.upload + clean: rm -rf $(subst md,html,$(wildcard *.md)) *.tmp rm -rf $(subst md,pdf,$(wildcard *.md)) rm -rf *.hex *.lst + diff --git a/chen.txt b/chen.txt new file mode 100644 index 0000000..49d8172 --- /dev/null +++ b/chen.txt @@ -0,0 +1,62 @@ +.equ PINA = 0x00 ; définition des adresses des ports +.equ DDRA = 0x01 +.equ PORTA = 0x02 +.equ PINB = 0x03 +.equ DDRB = 0x04 +.equ PORTB = 0x05 + +.equ RAMEND = 0x21FF +.equ SPH = 0x3E ; initialisation de la pile +.equ SPL = 0x3D + +.org 0x000 + ; Vecteur RESET + jmp debut + +.org 0x0080 + +debut: + ldi r16,0xFF ; On configure les ports A et B en sortie + out DDRA,r16 + out DDRB,r16 + r17 <- 0b00000001 ; 8 places de chenillard + + +boucleA: + ; On affiche l'état courant + out porta,r17 + + call tempo + + ; On calcule l'état suivant + lsl r17 + si r17 > 0 saut boucleA + + ; Si le bit "volant" est sorti de l'octet, on passe à l'autre partie du programme sur le port B + out porta,r17 ; On éteint le port A + ; On configure le registre pour qu'il commence de l'autre coté + r17 <- 0b10000000 + saut boucleB ; (pas nécessaire) + +boucleB: + out portb,r17 + + call tempo; + + lsr r17 + si r17 > 0 saut boucleB + + out portb,r17 + r17 <- 0b00000001 + saut boucleA + +; Programme pour faire une pause +tempo: + ; On fait une pause + ldi r24,8 +tempoA: + subi r22,1 + sbci r23,0 + sbci r24,0 + brcc tempoA + ret diff --git a/configure b/configure index 4ee686e..ba92ccb 100755 --- a/configure +++ b/configure @@ -26,13 +26,19 @@ fi echo "Vérification des dépendances pour la compilation des programmes Atmega 2560..." +if ! which wine &> /dev/null +then + echo "Veuillez installer avrdude (sudo apt-get install wine)" + exit 1 +fi + if ! which avrdude &> /dev/null then echo "Veuillez installer avrdude (sudo apt-get install avrdude)" exit 1 fi -echo "Installation des dépendances pour la compilation du compte-rendu..." +echo "Installation des bibliothèques pour la compilation du compte-rendu..." echo $(cd scripts; npm install) diff --git a/scripts/.gitignore b/scripts/.gitignore new file mode 100644 index 0000000..3c3629e --- /dev/null +++ b/scripts/.gitignore @@ -0,0 +1 @@ +node_modules diff --git a/scripts/Compilateur.exe b/scripts/Compilateur.exe new file mode 100644 index 0000000..82d4df8 Binary files /dev/null and b/scripts/Compilateur.exe differ diff --git a/scripts/gram.txt b/scripts/gram.txt new file mode 100644 index 0000000..a4d1674 --- /dev/null +++ b/scripts/gram.txt @@ -0,0 +1,791 @@ +% C'est un test + +% symbole + : 1 ou plus +% * : 0 ou plus +% pour absence de saut de ligne --> +% {NUMx} pour numérotation +% {SOURCE}ou {SOURCE-} pour le texte initial + +>main + +"Aide" +Bienvenue dans l'outil d'aide au codage +Traducteur version 1.0, B. CONRARD +Grammaire du 14/5/14 modifie pour IMA2A +modifié pour ROUSSEL et SUN + +[instruction]:inst + ; {SOURCE}{inst} + +>instruction + +[SymboleSi] [blanc]* [Expression]:exp [SymboleAlors] [instruction]:inst +{exp} TST R16 + BREQ eti{NUM0} +{inst}eti{NUM0}: + +[SymboleSi] [blanc]* [Expression]:exp [SymboleSaut] [Etiquette]:eti [blanc]* [fin] +{exp} TST R16 + BREQ eti{NUM0} + JMP {eti} +eti{NUM0}: + +[SymboleSi] [blanc]* [Expression]:exp [SymboleAppel] [Etiquette]:eti [blanc]* [fin] +{exp} TST R16 + BREQ eti{NUM0} + CALL {eti} +eti{NUM0}: + +[blanc]* [Registre]:regd [blanc]* [SymboleAffectation] [blanc]* [Registre]:regs [blanc]* [fin] + MOV {regd},{regs} + +[blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Registre]:regs [blanc]* [fin] + STS {var},{regs} + +[blanc]* [Registre]:regd [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] +{exp} MOV {regd},R16 + +[blanc]* [VariableIO]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] +{exp} OUT {var},R16 + +[blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* [fin] +{exp} STS {var},R16 + +[SymboleSaut] [Etiquette]:eti [blanc]* [fin] + JMP {eti} + +[SymboleAppel] [Etiquette]:eti [blanc]* [fin] + CALL {eti} + +>2ndeInst + +[blanc]* "," [blanc]* [Registre]:regd [blanc]* [SymboleAffectation] [blanc]* [Registre]:regs [blanc]* + MOV {regd},{regs} + +[blanc]* "," [blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Registre]:regs [blanc]* + STS {var},{regs} + +[blanc]* "," [blanc]* [Registre]:regd [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* +{exp} MOV {regd},R16 + +[blanc]* "," [blanc]* [VariableIO]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* +{exp} OUT {var},R16 + +[blanc]* "," [blanc]* [Variable]:var [blanc]* [SymboleAffectation] [blanc]* [Expression]:exp [blanc]* +{exp} STS {var},R16 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>fin + +";" [toutcar]* [finligne] +--> + +[finligne] +--> + +>toutcar + +[AlphaNum]:c +-->{c} + +[blanc] +--> + +'<>[]_{}@&~()-çà+éèù%"$£!:;.,?!':c +-->{c} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Expression + +[Expression5]:exp +-->{exp} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Expression5 + +[Expression25]:exp +-->{exp} + +%%%%%%%%%%%%%%%%%%%%% Operateur OU booleen + +>Expression25 + +[Expression30]:th [OpExpression25]*:calc +-->{th}{calc} + +>OpExpression25 + +[SymboleOuBool] [Expression30]:exp + TST R16 + BRNE eti{NUM0} +{exp}eti{NUM0}: + +%%%%%%%%%%%%%%%%%%%%% Operateur ET booleen + +>Expression30 + +[Expression35]:th [OpExpression30]*:calc +-->{th}{calc} + +>OpExpression30 + +[SymboleEtBool] [Expression35]:exp + TST R16 + BREQ eti{NUM0} +{exp}eti{NUM0}: + +%%%%%%%%%%%%%%%%%%%%% Comparaison + +>Expression35 + +[Expression40]:th [OpExpression35]*:calc +-->{th}{calc} + +>OpExpression35 + +[SymboleCmp]:symb [Expression45]:exp + PUSH R16 +{exp} POP R17 + CP R17,R16 + {symb} eti{NUM0} + CLR R16 + RJMP eti{NUM1} +eti{NUM0}: + LDI R16,0x01 +eti{NUM1}: + +[SymboleCmpSup] [Expression45]:exp + PUSH R16 +{exp} POP R17 + CP R17,R16 + BREQ eti{NUM0} + BRLO eti{NUM0} + LDI R16,0x01 + RJMP eti{NUM1} +eti{NUM0}: + CLR R16 +eti{NUM1}: + +[SymboleCmpInfEgal] [Expression45]:exp + PUSH R16 +{exp} POP R17 + CP R17,R16 + BREQ eti{NUM0} + BRLO eti{NUM0} + CLR R16 + RJMP eti{NUM1} +eti{NUM0}: + LDI R16,0x01 +eti{NUM1}: + +>SymboleCmp + +[SymboleCmpEgal] +-->BREQ + +[SymboleCmpDiff] +-->BRNE + +[SymboleCmpInf] +-->BRLO + +[SymboleCmpSupEgal] +-->BRSH + + +%%%%%%%%%%%%%%%%%%%%% OU Logique + +>Expression40 + +[Expression45]:th [OpExpression40]*:calc +-->{th}{calc} + +>OpExpression40 + +[SymboleOuLogique] [Registre]:reg [Expression45]- + OR R16,{reg} + +[SymboleOuLogique] [Valeur]:val [Expression45]- + ORI R16,{val} + +[SymboleOuLogique] [VariableIO]:var [Expression45]- + IN R17,{var} + OR R16,R17 + +[SymboleOuLogique] [Tableau]:var [Expression]:exp [blanc]* "]" [Expression45]- + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + OR R16,R17 + +[SymboleOuLogique] [Variable]:var [Expression45]- + LDS R17,{var} + OR R16,R17 + +[SymboleOuLogique] [Expression45]:exp + PUSH R16 +{exp} POP R17 + OR R16,R17 + +%%%%%%%%%%%%%%%%%%%%% ET Logique + +>Expression45 + +[Expression50]:th [OpExpression45]*:calc +-->{th}{calc} + +>OpExpression45 + +[SymboleEtLogique] [Registre]:reg [OpExpression50]- + AND R16,{reg} + +[SymboleEtLogique] [Valeur]:val [OpExpression50]- + ANDI R16,{val} + +[SymboleEtLogique] [VariableIO]:var [OpExpression50]- + IN R17,{var} + AND R16,R17 + +[SymboleEtLogique] [Tableau]:var [Expression]:exp [blanc]* "]" [OpExpression50]- + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + AND R16,R17 + +[SymboleEtLogique] [Variable]:var [OpExpression50]- + LDS R17,{var} + AND R16,R17 + +[SymboleEtLogique] [Expression50]:exp + PUSH R16 +{exp} POP R17 + AND R16,R17 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Expression50 + +[Expression60]:th [OpExpression50]*:calc +-->{th}{calc} + +>OpExpression50 + +[SymboleAddition] [Registre]:reg [OpExpression60]- + ADD R16,{reg} + +[SymboleAddition] [Valeur]:val [OpExpression60]- + LDI R17,{val} + ADD R16,R17 + +[SymboleAddition] [VariableIO]:var [OpExpression60]- + IN R17,{var} + ADD R16,R17 + +[SymboleAddition] [Tableau]:var [Expression]:exp [blanc]* "]" [OpExpression60]- + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + ADD R16,R17 + +[SymboleAddition] [Variable]:var [OpExpression60]- + LDS R17,{var} + ADD R16,R17 + +[SymboleAddition] [Expression60]:exp + PUSH R16 +{exp} POP R17 + ADD R16,R17 + +[SymboleSoustraction] [Registre]:reg [OpExpression60]- + SUB R16,{reg} + +[SymboleSoustraction] [Valeur]:val [OpExpression60]- + LDI R17,{val} + SUB R16,R17 + +[SymboleSoustraction] [VariableIO]:var [OpExpression60]- + IN R17,{var} + SUB R16,R17 + +[SymboleSoustraction] [Tableau]:var [Expression]:exp [blanc]* "]" [OpExpression60]- + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + SUB R16,R17 + +[SymboleSoustraction] [Variable]:var [OpExpression60]- + LDS R17,{var} + SUB R16,R17 + +[SymboleSoustraction] [Expression60]:exp + PUSH R16 +{exp} MOV R17,R16 + POP R16 + SUB R16,R17 + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Expression60 + +[Expression100]:th [OpExpression60]*:prod +-->{th}{prod} + +>OpExpression60 + +[SymboleMultiplier] [Registre]:reg + MUL R16,{reg} + MOV R16,R0 + +[SymboleMultiplier] [Valeur]:val + LDI R17,{val} + MUL R16,R17 + MOV R16,R0 + +[SymboleMultiplier] [VariableIO]:var + IN R17,{var} + MUL R16,R17 + MOV R16,R0 + +[SymboleMultiplier] [Tableau]:var [Expression]:exp [blanc]* "]" + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + MUL R16,R17 + MOV R16,R0 + +[SymboleMultiplier] [Variable]:var + LDS R17,{var} + MUL R16,R17 + MOV R16,R0 + +[SymboleMultiplier] [Expression100]:exp + PUSH R16 +{exp} POP R17 + MUL R16,R17 + MOV R16,R0 + +% diviser + +[SymboleDiviser] [Registre]:reg + MOV R17,{reg} + SER R18 +eti{NUM0}: + INC R18 + SUB R16,R17 + BRCC eti{NUM0} + MOV R16,R18 + +[SymboleDiviser] [Valeur]:val + LDI R17,{val} + SER R18 +eti{NUM0}: + INC R18 + SUB R16,R17 + BRCC eti{NUM0} + MOV R16,R18 + +[SymboleDiviser] [VariableIO]:var + IN R17,{var} + SER R18 +eti{NUM0}: + INC R18 + SUB R16,R17 + BRCC eti{NUM0} + MOV R16,R18 + +[SymboleDiviser] [Tableau]:var [Expression]:exp [blanc]* "]" + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 + SER R18 +eti{NUM0}: + INC R18 + SUB R16,R17 + BRCC eti{NUM0} + MOV R16,R18 + +[SymboleDiviser] [Variable]:var + LDS R17,{var} + SER R18 +eti{NUM0}: + INC R18 + SUB R16,R17 + BRCC eti{NUM0} + MOV R16,R18 + +[SymboleDiviser] [Expression100]:exp + PUSH R16 +{exp} POP R17 + SER R18 +eti{NUM0}: + INC R18 + SUB R17,R16 + BRCC eti{NUM0} + MOV R16,R18 + +% Modulo + +[SymboleModulo] [Registre]:reg + MOV R17,{reg} +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + +[SymboleModulo] [Valeur]:val + LDI R17,{val} +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + +[SymboleModulo] [VariableIO]:var + IN R17,{var} +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + +[SymboleModulo] [Tableau]:var [Expression]:exp [blanc]* "]" + PUSH R16 +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R17,X + POP R16 +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + +[SymboleModulo] [Variable]:var + LDS R17,{var} +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + +[SymboleModulo] [Expression100]:exp + PUSH R16 +{exp} MOV R17,R16 + POP R16 +eti{NUM0}: + SUB R16,R17 + BRCC eti{NUM0} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Expression100 + +[Terme]:th +-->{th} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Terme + +[Registre]:reg + MOV R16,{reg} + +[VariableIO]:var + IN R16,{var} + +[VariableROM]:var + LDI R30,low({var}<<1) + LDI R31,high({var}<<1) + LPM R16,Z + +[TableauROM]:var [Expression]:exp [blanc]* "]" +{exp} LDI R30,low({var}<<1) + LDI R31,high({var}<<1) + CLR R17 + ADD R30,R16 + ADC R31,R17 + LPM R16,Z + +[Tableau]:var [Expression]:exp [blanc]* "]" +{exp} LDI R26,low({var}) + LDI R27,high({var}) + CLR R17 + ADD R26,R16 + ADC R27,R17 + LD R16,X + +[Variable]:var + LDS R16,{var} + +[Valeur]:val + LDI R16,{val} + + +[blanc]* "(" [Expression]:exp [blanc]* ")" +-->{exp} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%% Variable %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>Registre + +[blanc]* 'Rr' '0123456789'+:id +-->R{id} + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@REG" "["- +-->{l1}{l2} + +>VariableIO + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@IO" +-->{l1}{l2} + +>VariableROM + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@ROM" "["- +-->{l1}{l2} + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@pgm" "["- +-->{l1}{l2} + +>Variable + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@"- +-->{l1}{l2} + +>Tableau + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "[" +-->{l1}{l2} + +>TableauROM + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@ROM[" +-->{l1}{l2} + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 "@pgm[" +-->{l1}{l2} + +>Valeur + +[blanc]* "0b" '01'+:val +-->0b{val} + +[blanc]* "0x" '0123456789abcdefABCDEF'+:val +-->0x{val} + +[blanc]* '0123456789'+:val +-->{val} + +[blanc]* "'" [toutcar]:car "'" +-->'{car}' + +>Etiquette + +[blanc]* [Alpha]:l1 [AlphaNum]*:l2 +-->{l1}{l2} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%% SYMBOLE %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +>SymboleAppel + +[blanc]* "appel" +--> + + +>SymboleSaut + +[blanc]* "saut" +--> + +[blanc]* "goto" +--> + +[blanc]* "jump" +--> + +>SymboleSi + +[blanc]* "si" +--> + +[blanc]* "if" +--> + +[blanc]* "SI" +--> + +[blanc]* "IF" +--> + +>SymboleAlors + +[blanc]* "then" +--> + +[blanc]* "alors" +--> + +[blanc]* "THEN" +--> + +[blanc]* "ALORS" +--> + +>SymboleSeparateur + +[blanc]* "," +--> + +>SymboleEtBool + +[blanc]* "&&" +--> + +[blanc]* "et" +--> + +>SymboleOuBool + +[blanc]* "||" +--> + +[blanc]* "ou" +--> + +>SymboleCmpInf + +[blanc]* "<" +--> + +>SymboleCmpInfEgal + +[blanc]* "<=" +--> + +>SymboleCmpSup + +[blanc]* ">" +--> + +>SymboleCmpSupEgal + +[blanc]* ">=" +--> + +>SymboleCmpDiff + +[blanc]* "!=" +--> + +[blanc]* "<>" +--> + +>SymboleCmpEgal + +[blanc]* "==" +--> + +[blanc]* "=" +--> + +>SymboleEtLogique + +[blanc]* "&" +--> + +>SymboleOuLogique + +[blanc]* "|" +--> + +>SymboleDiviser + +[blanc]* "/" +--> + +>SymboleModulo + +[blanc]* "%" +--> + +>SymboleMultiplier + +[blanc]* "*" +--> + +>SymboleOuBool + +[blanc]* "ou" +--> + +>SymboleAddition + +[blanc]* "+" +--> + +>SymboleSoustraction + +[blanc]* "-" +--> + +>SymboleAffectation + +[blanc]* "<-" +--> + +[blanc]* "=" +--> + +>Alpha + +'abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ_':lettre +-->{lettre} + +>AlphaNum + +'abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789_':lettre +-->{lettre} + +>Num + +'0123456789'+:val +-->{val} + +>blanc + +" " +--> + +[tabulation] +--> + + -- libgit2 0.21.2