/* * Copyright (C) 2016 Phytec Messtechnik GmbH * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. * * The description of the registers was extracted from the * Reference Manual MKW2xDxxxRM.pdf. After the release of MCR20A Device, * it was extended by the undocumented registers from the file MCR20reg.h. * * Portions of this file are derived from material that is * Copyright (c) 2015, Freescale Semiconductor, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /** * @ingroup drivers_kw2xrf * @{ * * @file * @brief Register and command definitions for the MKW2XD Modem * * @author Johann Fischer */ #ifndef KW2XRF_REG_H #define KW2XRF_REG_H #ifdef __cplusplus extern "C" { #endif /** Option to for SPI-IF to read a register */ #define MKW2XDRF_REG_READ (uint8_t)(1 << 7) /** Option to for SPI-IF to write a register */ #define MKW2XDRF_REG_WRITE (uint8_t)(0) /** Option to for SPI-IF to read data from the RX/TX-Buffer */ #define MKW2XDRF_BUF_READ (uint8_t)(1 << 7 | 1 << 6) /** Option to for SPI-IF to write data to RX/TX-Buffer */ #define MKW2XDRF_BUF_WRITE (uint8_t)(1 << 6) /** Option for SPI-IF */ #define MKW2XDRF_BUF_BYTE_READ (uint8_t)(1 << 7 | 1 << 6 | 1 << 5) /** Option for SPI-IF */ #define MKW2XDRF_BUF_BYTE_WRITE (uint8_t)(1 << 6 | 1 << 5) /** Transceiver Sequence Selector, define Values for XCVSEQ */ typedef enum { XCVSEQ_IDLE = 0, XCVSEQ_RECEIVE, XCVSEQ_TRANSMIT, XCVSEQ_CCA, XCVSEQ_TX_RX, XCVSEQ_CONTINUOUS_CCA, } kw2xrf_physeq_t; enum mkw2xdrf_dregister { MKW2XDM_IRQSTS1 = 0x0, /**< Interrupt Request Status 1 */ MKW2XDM_IRQSTS2 = 0x1, /**< Interrupt Request Status 2 */ MKW2XDM_IRQSTS3 = 0x2, /**< Interrupt Request Status 3 */ MKW2XDM_PHY_CTRL1 = 0x3, /**< PHY Control 1 */ MKW2XDM_PHY_CTRL2 = 0x4, /**< PHY Control 2 */ MKW2XDM_PHY_CTRL3 = 0x5, /**< PHY Control 3 */ MKW2XDM_RX_FRM_LEN = 0x6, /**< Receive Frame Length */ MKW2XDM_PHY_CTRL4 = 0x7, /**< PHY Control 4 */ MKW2XDM_SRC_CTRL = 0x8, /**< SRC Control */ MKW2XDM_SRC_ADDRS_SUM_LSB = 0x9, /**< SRC Address SUM LSB */ MKW2XDM_SRC_ADDRS_SUM_MSB = 0xa, /**< SRC Address SUM MSB */ MKW2XDM_CCA1_ED_FNL = 0xb, /**< CCA1 ED FNL */ MKW2XDM_EVENT_TIMER_LSB = 0xc, /**< Event Timer LSB */ MKW2XDM_EVENT_TIMER_MSB = 0xd, /**< Event Timer MSB */ MKW2XDM_EVENT_TIMER_USB = 0xe, /**< Event Timer USB */ MKW2XDM_TIMESTAMP_LSB = 0xf, /**< Timestamp LSB */ MKW2XDM_TIMESTAMP_MSB = 0x10, /**< Timestamp MSB */ MKW2XDM_TIMESTAMP_USB = 0x11, /**< Timestamp USB */ MKW2XDM_T3CMP_LSB = 0x12, /**< Timer 3 Compare Value LSB */ MKW2XDM_T3CMP_MSB = 0x13, /**< Timer 3 Compare Value MSB */ MKW2XDM_T3CMP_USB = 0x14, /**< Timer 3 Compare Value USB */ MKW2XDM_T2PRIMECMP_LSB = 0x15, /**< Timer 2-Prime Compare Value LSB */ MKW2XDM_T2PRIMECMP_MSB = 0x16, /**< Timer 2-Prime Compare Value MSB */ MKW2XDM_T1CMP_LSB = 0x17, /**< Timer 1 Compare Value LSB */ MKW2XDM_T1CMP_MSB = 0x18, /**< Timer 1 Compare Value MSB */ MKW2XDM_T1CMP_USB = 0x19, /**< Timer 1 Compare Value USB */ MKW2XDM_T2CMP_LSB = 0x1a, /**< Timer 2 Compare Value LSB */ MKW2XDM_T2CMP_MSB = 0x1b, /**< Timer 2 Compare Value MSB */ MKW2XDM_T2CMP_USB = 0x1c, /**< Timer 2 Compare Value USB */ MKW2XDM_T4CMP_LSB = 0x1d, /**< Timer 4 Compare Value LSB */ MKW2XDM_T4CMP_MSB = 0x1e, /**< Timer 4 Compare Value MSB */ MKW2XDM_T4CMP_USB = 0x1f, /**< Timer 4 Compare Value USB */ MKW2XDM_PLL_INT0 = 0x20, /**< PLL Integer Value for PAN0 */ MKW2XDM_PLL_FRAC0_LSB = 0x21, /**< PLL Frequency Fractional Value for PAN0 */ MKW2XDM_PLL_FRAC0_MSB = 0x22, /**< PLL Frequency Fractional Value for PAN0 */ MKW2XDM_PA_PWR = 0x23, /**< PA Power Control (PA_PWR) */ MKW2XDM_SEQ_STATE = 0x24, /**< Sequence Manager State */ MKW2XDM_LQI_VALUE = 0x25, /**< Link Quality Indicator */ MKW2XDM_RSSI_CCA_CNT = 0x26, /**< RSSI CCA CNT */ MKW2XDM_ASM_CTRL1 = 0x28, MKW2XDM_ASM_CTRL2 = 0x29, MKW2XDM_ASM_DATA_0 = 0x2A, MKW2XDM_ASM_DATA_1 = 0x2B, MKW2XDM_ASM_DATA_2 = 0x2C, MKW2XDM_ASM_DATA_3 = 0x2D, MKW2XDM_ASM_DATA_4 = 0x2E, MKW2XDM_ASM_DATA_5 = 0x2F, MKW2XDM_ASM_DATA_6 = 0x30, MKW2XDM_ASM_DATA_7 = 0x31, MKW2XDM_ASM_DATA_8 = 0x32, MKW2XDM_ASM_DATA_9 = 0x33, MKW2XDM_ASM_DATA_A = 0x34, MKW2XDM_ASM_DATA_B = 0x35, MKW2XDM_ASM_DATA_C = 0x36, MKW2XDM_ASM_DATA_D = 0x37, MKW2XDM_ASM_DATA_E = 0x38, MKW2XDM_ASM_DATA_F = 0x39, MKW2XDM_OVERWRITE_VER = 0x3b, /**< Overwrite Version Number */ MKW2XDM_CLK_OUT_CTRL = 0x3c, /**< CLK_OUT Control */ MKW2XDM_PWR_MODES = 0x3d, /**< Power Modes */ MKW2XDM_IAR_INDEX = 0x3e, /**< IAR Index */ MKW2XDM_IAR_DATA = 0x3f, /**< IAR Data */ }; #define MKW2XDM_IRQSTS1_RX_FRM_PEND (1 << 7) #define MKW2XDM_IRQSTS1_PLL_UNLOCK_IRQ (1 << 6) #define MKW2XDM_IRQSTS1_FILTERFAIL_IRQ (1 << 5) #define MKW2XDM_IRQSTS1_RXWTRMRKIRQ (1 << 4) #define MKW2XDM_IRQSTS1_CCAIRQ (1 << 3) #define MKW2XDM_IRQSTS1_RXIRQ (1 << 2) #define MKW2XDM_IRQSTS1_TXIRQ (1 << 1) #define MKW2XDM_IRQSTS1_SEQIRQ (1 << 0) #define MKW2XDM_IRQSTS2_CRCVALID (1 << 7) #define MKW2XDM_IRQSTS2_CCA (1 << 6) #define MKW2XDM_IRQSTS2_SRCADDR (1 << 5) #define MKW2XDM_IRQSTS2_PI (1 << 4) #define MKW2XDM_IRQSTS2_TMRSTATUS (1 << 3) #define MKW2XDM_IRQSTS2_PB_ERR_IRQ (1 << 1) #define MKW2XDM_IRQSTS2_WAKE_IRQ (1 << 0) #define MKW2XDM_IRQSTS3_TMR4MSK (1 << 7) #define MKW2XDM_IRQSTS3_TMR3MSK (1 << 6) #define MKW2XDM_IRQSTS3_TMR2MSK (1 << 5) #define MKW2XDM_IRQSTS3_TMR1MSK (1 << 4) #define MKW2XDM_IRQSTS3_TMR4IRQ (1 << 3) #define MKW2XDM_IRQSTS3_TMR3IRQ (1 << 2) #define MKW2XDM_IRQSTS3_TMR2IRQ (1 << 1) #define MKW2XDM_IRQSTS3_TMR1IRQ (1 << 0) #define MKW2XDM_IRQSTS3_TMR_IRQ_MASK 0xfu #define MKW2XDM_IRQSTS3_TMR_IRQ_SHIFT 0x0u #define MKW2XDM_IRQSTS3_TMR_IRQ(x) (((uint8_t)(((uint8_t)(x))<