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RIOT/cpu/saml21/include/periph_cpu.h 2.48 KB
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  /*
   * Copyright (C) 2015-2016 Freie Universitรคt Berlin
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @ingroup         cpu_saml21
   * @brief           CPU specific definitions for internal peripheral handling
   * @{
   *
   * @file
   * @brief           CPU specific definitions for internal peripheral handling
   *
   * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
   */
  
  #ifndef PERIPH_CPU_H
  #define PERIPH_CPU_H
  
  #include "periph_cpu_common.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @brief   Mapping of pins to EXTI lines, -1 means not EXTI possible
   */
  static const int8_t exti_config[2][32] = {
      { 0,  1,  2,  3,  4,  5,  6,  7, -1,  9, 10, 11, 12, 13, 14, 15,
        0,  1,  2,  3,  4,  5,  6,  7, 12, 13, -1, 15, -1, -1, 10, 11},
      { 0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,
        0,  1, -1, -1, -1, -1,  6,  7, -1, -1, -1, -1, -1, -1, 14, 15},
  };
  
  /**
   * @brief   Available ports on the SAML21 for convenient access
   */
  enum {
      PA = 0,                 /**< port A */
      PB = 1,                 /**< port B */
  };
  
  /**
   * @brief   Generate GPIO mode bitfields
   *
   * We use 3 bit to determine the pin functions:
   * - bit 0: PU or PU
   * - bit 1: input enable
   * - bit 2: pull enable
   */
  #define GPIO_MODE(pr, ie, pe)   (pr | (ie << 1) | (pe << 2))
  
  #ifndef DOXYGEN
  /**
   * @brief   Override GPIO modes
   * @{
   */
  #define HAVE_GPIO_MODE_T
  typedef enum {
      GPIO_IN    = GPIO_MODE(0, 1, 0),    /**< IN */
      GPIO_IN_PD = GPIO_MODE(0, 1, 1),    /**< IN with pull-down */
      GPIO_IN_PU = GPIO_MODE(1, 1, 1),    /**< IN with pull-up */
      GPIO_OUT   = GPIO_MODE(0, 0, 0),    /**< OUT (push-pull) */
      GPIO_OD    = 0xfe,                  /**< not supported by HW */
      GPIO_OD_PU = 0xff                   /**< not supported by HW */
  } gpio_mode_t;
  /** @} */
  #endif /* ndef DOXYGEN */
  
  #define HAVE_ADC_RES_T
  typedef enum {
      ADC_RES_6BIT  = 0xff,                       /**< not supported */
      ADC_RES_8BIT  = ADC_CTRLC_RESSEL_8BIT,      /**< ADC resolution: 8 bit */
      ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT,     /**< ADC resolution: 10 bit */
      ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT,     /**< ADC resolution: 12 bit */
      ADC_RES_14BIT = 0xfe,                       /**< not supported */
      ADC_RES_16BIT = 0xfd                        /**< not supported */
  } adc_res_t;
  /** @} */
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CPU_H */
  /** @} */