a752c7ab
 elopes
add first test an...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/*
* Copyright (C) 2016 Leon George
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc26x0
* @{
*
* @file
* @brief Interrupt vector definitions
*
* @author Leon M. George <leon@georgemail.eu>
*/
#include <stdint.h>
#include "cpu.h"
#include "board.h"
#include "vectors_cortexm.h"
/* get the start of the ISR stack as defined in the linkerscript */
extern uint32_t _estack;
/* define a local dummy handler as it needs to be in the same compilation unit
* as the alias definition */
void dummy_handler(void) {
dummy_handler_default();
}
/* CC26x0 specific interrupt vectors */
WEAK_DEFAULT void isr_edge(void);
WEAK_DEFAULT void isr_i2c(void);
WEAK_DEFAULT void isr_rfc_cpe1(void);
WEAK_DEFAULT void isr_aon_rx_tx_cs(void);
WEAK_DEFAULT void isr_aon_rtc(void);
WEAK_DEFAULT void isr_uart(void);
WEAK_DEFAULT void isr_scse0_aon(void);
WEAK_DEFAULT void isr_ssi0(void);
WEAK_DEFAULT void isr_ssi1(void);
WEAK_DEFAULT void isr_rfc_cpe0(void);
WEAK_DEFAULT void isr_rfc_hw(void);
WEAK_DEFAULT void isr_rfc_cmd_ack(void);
WEAK_DEFAULT void isr_i2s(void);
WEAK_DEFAULT void isr_scse1_aon(void);
WEAK_DEFAULT void isr_watchdog(void);
WEAK_DEFAULT void isr_timer0_chan0(void);
WEAK_DEFAULT void isr_timer0_chan1(void);
WEAK_DEFAULT void isr_timer1_chan0(void);
WEAK_DEFAULT void isr_timer1_chan1(void);
WEAK_DEFAULT void isr_timer2_chan0(void);
WEAK_DEFAULT void isr_timer2_chan1(void);
WEAK_DEFAULT void isr_timer3_chan0(void);
WEAK_DEFAULT void isr_timer3_chan1(void);
WEAK_DEFAULT void isr_crypto_res(void);
WEAK_DEFAULT void isr_dma(void);
WEAK_DEFAULT void isr_dmaerr(void);
WEAK_DEFAULT void isr_flash(void);
WEAK_DEFAULT void isr_se0(void);
WEAK_DEFAULT void isr_aux_ce(void);
WEAK_DEFAULT void isr_aon_prog(void);
WEAK_DEFAULT void isr_dyn_prog(void);
WEAK_DEFAULT void isr_comp(void);
WEAK_DEFAULT void isr_adc(void);
WEAK_DEFAULT void isr_trng(void);
/* CPU specific interrupt vector table */
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
isr_edge, /* 16 AON edge detect */
isr_i2c, /* 17 I2C */
isr_rfc_cpe1, /* 18 RF Command and Packet Engine 1 */
isr_aon_rx_tx_cs, /* 19 AON SpiSplave Rx, Tx and CS */
isr_aon_rtc, /* 20 AON RTC */
isr_uart, /* 21 UART0 Rx and Tx */
isr_scse0_aon, /* 22 Sensor Controller software event 0, through AON domain */
isr_ssi0, /* 23 SSI0 Rx and Tx */
isr_ssi1, /* 24 SSI1 Rx and Tx */
isr_rfc_cpe0, /* 25 RF Command and Packet Engine 0 */
isr_rfc_hw, /* 26 RF Core Hardware */
isr_rfc_cmd_ack, /* 27 RF Core Command Acknowledge */
isr_i2s, /* 28 I2S */
isr_scse1_aon, /* 29 Sensor Controller software event 1, through AON domain */
isr_watchdog, /* 30 Watchdog timer */
isr_timer0_chan0, /* 31 Timer 0 subtimer A */
isr_timer0_chan1, /* 32 Timer 0 subtimer B */
isr_timer1_chan0, /* 33 Timer 1 subtimer A */
isr_timer1_chan1, /* 34 Timer 1 subtimer B */
isr_timer2_chan0, /* 35 Timer 2 subtimer A */
isr_timer2_chan1, /* 36 Timer 2 subtimer B */
isr_timer3_chan0, /* 37 Timer 3 subtimer A */
isr_timer3_chan1, /* 38 Timer 3 subtimer B */
isr_crypto_res, /* 39 Crypto Core Result available */
isr_dma, /* 40 uDMA Software */
isr_dmaerr, /* 41 uDMA Error */
isr_flash, /* 42 Flash controller */
isr_se0, /* 43 Software Event 0 */
isr_aux_ce, /* 44 AUX combined event, directly to MCU domain */
isr_aon_prog, /* 45 AON programmable 0 */
isr_dyn_prog, /* 46 Dynamic Programmable interrupt (default source: PRCM) */
isr_comp, /* 47 AUX Comparator A */
isr_adc, /* 48 AUX ADC IRQ */
isr_trng, /* 49 TRNG event */
};
/** @} */
|