a752c7ab
 elopes
add first test an...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
/*
* Copyright (C) 2014 Freie Universitรคt Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_stm32l1 STM32L1
* @brief CPU specific implementations for the STM32F1
* @ingroup cpu
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#include "cpu_conf_common.h"
/**
* @brief STM32 L1 cpu type
*
* From CMSIS header file, allowed values for L1 cpu types are:
* * STM32L1XX_MD:
* * Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
* STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
* STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
* SM32L152x8xxA and STM32L152xBxxA.
* * Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
* STM32L100x8xx and STM32L100xBxx.
*
* * STM32L1XX_MDP:
* * Ultra Low Power Medium-density Plus devices: STM32L151xCxx,
* STM32L152xCxx and STM32L162xCxx
* * Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx
*
* * STM32L1XX_HD: Ultra Low Power High-density devices: STM32L151xDxx,
* STM32L152xDxx and STM32L162xDxx
*
* * STM32L1XX_XL: Ultra Low Power XL-density devices: STM32L151xExx,
* STM32L152xExx and STM32L162xExx
*/
#if defined(CPU_MODEL_STM32L151RBA)
#define STM32L1XX_MD (1U)
#elif defined(CPU_MODEL_STM32L151RC)
#define STM32L1XX_MDP (1U)
#else
#define STM32L1XX_XL (1U)
#endif
#include "vendor/stm32l1xx.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(CPU_MODEL_STM32L151RBA)
#define CPU_IRQ_NUMOF (45U)
#else
#define CPU_IRQ_NUMOF (57U)
#endif
#define CPU_FLASH_BASE FLASH_BASE
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */
/** @} */
|