a752c7ab
 elopes
add first test an...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
|
/*
* Copyright(C) 2017 Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup cpu_mips_pic32_common
* @ingroup drivers_periph_gpio
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @}
*/
#include <assert.h>
#include <stdint.h>
#include "periph/gpio.h"
#include "board.h"
#define GPIO_PIN_NO(PIN) (1 << ((PIN) & 0xf))
#define GPIO_PORT(PIN) ((PIN) >> 4)
#define LATx(P) (base_address[P].gpio[0x10/0x4])
#define LATxCLR(P) (base_address[P].gpio[0x14/0x4])
#define LATxSET(P) (base_address[P].gpio[0x18/0x4])
#define LATxINV(P) (base_address[P].gpio[0x1C/0x4])
#define PORTx(P) (base_address[P].gpio[0x0])
#define CNPUxCLR(P) (base_address[P].gpio[0x34/0x4])
#define CNPUxSET(P) (base_address[P].gpio[0x38/0x4])
#define CNPDxCLR(P) (base_address[P].gpio[0x44/0x4])
#define CNPDxSET(P) (base_address[P].gpio[0x48/0x4])
#define ODCxCLR(P) (base_address[P].gpio[0x24/0x4])
#define ODCxSET(P) (base_address[P].gpio[0x28/0x4])
#define ANSELxCLR(P) (base_address[P].ansel[0x04/0x4])
#define TRISxCLR(P) (base_address[P].tris[0x04/0x4])
#define TRISxSET(P) (base_address[P].tris[0x08/0x4])
typedef struct PIC32_GPIO_tag {
volatile uint32_t* gpio;
volatile uint32_t* ansel;
volatile uint32_t* tris;
} PIC32_GPIO_T;
static PIC32_GPIO_T base_address[] = {
#ifdef _PORTA_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTA_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELA,
.tris = (volatile uint32_t*)&TRISA
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTB_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTB_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELB,
.tris = (volatile uint32_t*)&TRISB
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTC_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTC_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELC,
.tris = (volatile uint32_t*)&TRISC
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTD_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTD_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELD,
.tris = (volatile uint32_t*)&TRISD
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTE_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTE_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELE,
.tris = (volatile uint32_t*)&TRISE
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTF_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTF_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELF,
.tris = (volatile uint32_t*)&TRISF
},
#else
{0 , 0, 0},
#endif
#ifdef _PORTG_BASE_ADDRESS
{
.gpio = (volatile uint32_t*)_PORTG_BASE_ADDRESS,
.ansel = (volatile uint32_t*)&ANSELG,
.tris = (volatile uint32_t*)&TRISG
},
#else
{0 , 0, 0},
#endif
};
static inline int check_valid_port(uint8_t port)
{
return port < (sizeof(base_address)/sizeof(base_address[0]))
&& base_address[port].gpio != NULL;
}
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
uint8_t port = GPIO_PORT(pin);
uint32_t pin_no = GPIO_PIN_NO(pin);
uint8_t output = 0, pu = 0, pd = 0, od = 0;
assert(check_valid_port(port));
switch (mode) {
case GPIO_IN:
break;
case GPIO_IN_PD:
pd = 1;
break;
case GPIO_IN_PU:
pu = 1;
break;
case GPIO_OD_PU:
pu = 1;
case GPIO_OD:
od = 1;
case GPIO_OUT:
output = 1;
break;
}
ANSELxCLR(port) = pin_no; /* Configure GPIO as digital */
if (pu)
CNPUxSET(port) = pin_no;
else
CNPUxCLR(port) = pin_no;
if (pd)
CNPDxSET(port) = pin_no;
else
CNPDxCLR(port) = pin_no;
if (od)
ODCxSET(port) = pin_no;
else
ODCxCLR(port) = pin_no;
if (output)
TRISxCLR(port) = pin_no;
else
TRISxSET(port) = pin_no;
return 0;
}
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
(void)pin;
(void)mode;
(void)flank;
(void)cb;
(void)arg;
/* TODO: Not implemented yet */
return -1;
}
int gpio_read(gpio_t pin)
{
assert(check_valid_port(GPIO_PORT(pin)));
return PORTx(GPIO_PORT(pin)) & GPIO_PIN_NO(pin);
}
void gpio_set(gpio_t pin)
{
assert(check_valid_port(GPIO_PORT(pin)));
LATxSET(GPIO_PORT(pin)) = GPIO_PIN_NO(pin);
}
void gpio_clear(gpio_t pin)
{
assert(check_valid_port(GPIO_PORT(pin)));
LATxCLR(GPIO_PORT(pin)) = GPIO_PIN_NO(pin);
}
void gpio_toggle(gpio_t pin)
{
assert(check_valid_port(GPIO_PORT(pin)));
LATxINV(GPIO_PORT(pin)) = GPIO_PIN_NO(pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value)
gpio_set(pin);
else
gpio_clear(pin);
}
|