a752c7ab
 elopes
add first test an...
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_mips32r2_commom
* @{
*
* @file
* @brief API for supporting External Interrupt Controllers (EIC mode)
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef EIC_IRQ_H
#define EIC_IRQ_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ brief Internal Interrupt numbers
*
* MIPS cores have a few internally generated interrupts from the Timer,
* Performance Counters and Fast Debug Channel hardware, in EIC mode these
* become outputs from the core and are connected to the external controller,
* the external control then loops these back at whichever IPL it decides
*
* We use negative numbers to represent these, leaving positive numbers free for
* the SoC specific interrupts
* @{
*/
#define EIC_IRQ_TIMER (-1)
#define EIC_IRQ_FDC (-2)
#define EIC_IRQ_PC (-3)
/** @} */
/**
* @brief Configure and route the interrupt
*/
void eic_irq_configure(int irq_num);
/**
* @brief Enable an interrupt
*/
void eic_irq_enable(int irq_num);
/**
* @brief Disable an interrupt
*/
void eic_irq_disable(int irq_num);
/**
* @brief Acknowledge an interrupt
*/
void eic_irq_ack(int irq_num);
#ifdef __cplusplus
}
#endif
#endif /* EIC_IRQ_H */
/** @} */
|