Blame view

RIOT/boards/sodaq-explorer/include/periph_conf.h 7.33 KB
a752c7ab   elopes   add first test an...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
  /*
   * Copyright (C)  2017 Inria
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @ingroup     boards_sodaq-explorer
   * @{
   *
   * @file
   * @brief       Configuration of CPU peripherals for the Sodaq LoRaWAN Explorer board
   *
   * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
   */
  
  #ifndef PERIPH_CONF_H
  #define PERIPH_CONF_H
  
  #include "periph_cpu.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @name    External oscillator and clock configuration
   *
   * For selection of the used CORECLOCK, we have implemented two choices:
   *
   * - usage of the PLL fed by the internal 8MHz oscillator divided by 8
   * - usage of the internal 8MHz oscillator directly, divided by N if needed
   *
   *
   * The PLL option allows for the usage of a wider frequency range and a more
   * stable clock with less jitter. This is why we use this option as default.
   *
   * The target frequency is computed from the PLL multiplier and the PLL divisor.
   * Use the following formula to compute your values:
   *
   * CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
   *
   * NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
   *       frequency is 96MHz. So PLL_MULL must be between 31 and 95!
   *
   *
   * The internal Oscillator used directly can lead to a slightly better power
   * efficiency to the cost of a less stable clock. Use this option when you know
   * what you are doing! The actual core frequency is adjusted as follows:
   *
   * CORECLOCK = 8MHz / DIV
   *
   * NOTE: A core clock frequency below 1MHz is not recommended
   *
   * @{
   */
  #define CLOCK_USE_PLL       (1)
  
  #if CLOCK_USE_PLL
  /* edit these values to adjust the PLL output frequency */
  #define CLOCK_PLL_MUL       (47U)               /* must be >= 31 & <= 95 */
  #define CLOCK_PLL_DIV       (1U)                /* adjust to your needs */
  /* generate the actual used core clock frequency */
  #define CLOCK_CORECLOCK     (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
  #else
  /* edit this value to your needs */
  #define CLOCK_DIV           (1U)
  /* generate the actual core clock frequency */
  #define CLOCK_CORECLOCK     (8000000 / CLOCK_DIV)
  #endif
  /** @} */
  
  /**
   * @name Timer peripheral configuration
   * @{
   */
  #define TIMER_NUMOF         (2U)
  #define TIMER_0_EN          1
  #define TIMER_1_EN          1
  
  /* Timer 0 configuration */
  #define TIMER_0_DEV         TC3->COUNT16
  #define TIMER_0_CHANNELS    2
  #define TIMER_0_MAX_VALUE   (0xffff)
  #define TIMER_0_ISR         isr_tc3
  
  /* Timer 1 configuration */
  #define TIMER_1_DEV         TC4->COUNT32
  #define TIMER_1_CHANNELS    2
  #define TIMER_1_MAX_VALUE   (0xffffffff)
  #define TIMER_1_ISR         isr_tc4
  /** @} */
  
  /**
   * @name UART configuration
   * @{
   */
  static const uart_conf_t uart_config[] = {
      {
          .dev      = &SERCOM5->USART,
          .rx_pin   = GPIO_PIN(PB,31),  /* D0, RX Pin */
          .tx_pin   = GPIO_PIN(PB,30),  /* D1, TX Pin */
          .mux      = GPIO_MUX_D,
          .rx_pad   = UART_PAD_RX_1,
          .tx_pad   = UART_PAD_TX_0_RTS_2_CTS_3,
          .flags    = UART_FLAG_NONE,
          .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
      },
      {
          .dev      = &SERCOM4->USART,
          .rx_pin   = GPIO_PIN(PB,13),
          .tx_pin   = GPIO_PIN(PB,14),
          .mux      = GPIO_MUX_C,
          .rx_pad   = UART_PAD_RX_1,
          .tx_pad   = UART_PAD_TX_2,
          .flags    = UART_FLAG_NONE,
          .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
      },
      { /* Connected to RN2483 */
          .dev      = &SERCOM0->USART,
          .rx_pin   = GPIO_PIN(PA,5),
          .tx_pin   = GPIO_PIN(PA,6),
          .mux      = GPIO_MUX_D,
          .rx_pad   = UART_PAD_RX_1,
          .tx_pad   = UART_PAD_TX_2,
          .flags    = UART_FLAG_NONE,
          .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
      },
  };
  
  /* interrupt function name mapping */
  #define UART_0_ISR          isr_sercom5
  #define UART_1_ISR          isr_sercom4
  #define UART_2_ISR          isr_sercom0
  
  #define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
  /** @} */
  
  /**
   * @name ADC configuration
   * @{
   */
  #define ADC_0_EN                           1
  #define ADC_MAX_CHANNELS                   17
  /* ADC 0 device configuration */
  #define ADC_0_DEV                          ADC
  #define ADC_0_IRQ                          ADC_IRQn
  
  /* ADC 0 Default values */
  #define ADC_0_CLK_SOURCE                   0 /* GCLK_GENERATOR_0 */
  #define ADC_0_PRESCALER                    ADC_CTRLB_PRESCALER_DIV512
  
  #define ADC_0_NEG_INPUT                    ADC_INPUTCTRL_MUXNEG_GND
  #define ADC_0_GAIN_FACTOR_DEFAULT          ADC_INPUTCTRL_GAIN_1X
  #define ADC_0_REF_DEFAULT                  ADC_REFCTRL_REFSEL_INT1V
  
  static const adc_conf_chan_t adc_channels[] = {
      /* port, pin, muxpos */
      {GPIO_PIN(PB, 0), ADC_INPUTCTRL_MUXPOS_PIN8},     /* A0 */
      {GPIO_PIN(PB, 1), ADC_INPUTCTRL_MUXPOS_PIN9},     /* A1 */
      {GPIO_PIN(PB, 2), ADC_INPUTCTRL_MUXPOS_PIN10},    /* A2 */
      {GPIO_PIN(PB, 3), ADC_INPUTCTRL_MUXPOS_PIN11},    /* A3 */
      {GPIO_PIN(PA, 8), ADC_INPUTCTRL_MUXPOS_PIN16},    /* A4 */
      {GPIO_PIN(PA, 9), ADC_INPUTCTRL_MUXPOS_PIN17},    /* A5 */
      {GPIO_PIN(PA, 4), ADC_INPUTCTRL_MUXPOS_PIN4},     /* A6 (temperature) */
  };
  
  #define ADC_0_CHANNELS                     (7U)
  #define ADC_NUMOF                          ADC_0_CHANNELS
  /** @} */
  
  /**
   * @name SPI configuration
   * @{
   */
  static const spi_conf_t spi_config[] = {
      {
          .dev      = &SERCOM3->SPI,
          .miso_pin = GPIO_PIN(PA, 22),
          .mosi_pin = GPIO_PIN(PA, 20),
          .clk_pin  = GPIO_PIN(PA, 21),
          .miso_mux = GPIO_MUX_C,
          .mosi_mux = GPIO_MUX_C,
          .clk_mux  = GPIO_MUX_C,
          .miso_pad = SPI_PAD_MISO_0,
          .mosi_pad = SPI_PAD_MOSI_2_SCK_3
      }
  };
  
  #define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
  /** @} */
  
  /**
   * @name I2C configuration
   * @{
   */
  #define I2C_NUMOF          (2U)
  #define I2C_0_EN            1
  #define I2C_1_EN            1
  #define I2C_2_EN            0
  #define I2C_3_EN            0
  #define I2C_IRQ_PRIO        1
  
  #define I2C_0_DEV           SERCOM1->I2CM
  #define I2C_0_IRQ           SERCOM1_IRQn
  #define I2C_0_ISR           isr_sercom1
  /* I2C 0 GCLK */
  #define I2C_0_GCLK_ID       SERCOM1_GCLK_ID_CORE
  #define I2C_0_GCLK_ID_SLOW  SERCOM1_GCLK_ID_SLOW
  /* I2C 0 pin configuration */
  #define I2C_0_SDA           GPIO_PIN(PA, 16)
  #define I2C_0_SCL           GPIO_PIN(PA, 17)
  #define I2C_0_MUX           GPIO_MUX_C
  
  #define I2C_1_DEV           SERCOM2->I2CM
  #define I2C_1_IRQ           SERCOM2_IRQn
  #define I2C_1_ISR           isr_sercom2
  /* I2C 1 GCLK */
  #define I2C_1_GCLK_ID       SERCOM2_GCLK_ID_CORE
  #define I2C_1_GCLK_ID_SLOW  SERCOM2_GCLK_ID_SLOW
  /* I2C 1 pin configuration */
  #define I2C_1_SDA           GPIO_PIN(PA, 8)
  #define I2C_1_SCL           GPIO_PIN(PA, 9)
  #define I2C_1_MUX           GPIO_MUX_C
  /** @} */
  
  /**
   * @name RTC configuration
   * @{
   */
  #define RTC_NUMOF           (1U)
  #define RTC_DEV             RTC->MODE2
  /** @} */
  
  /**
   * @name RTT configuration
   * @{
   */
  #define RTT_NUMOF           (1U)
  #define RTT_DEV             RTC->MODE0
  #define RTT_IRQ             RTC_IRQn
  #define RTT_IRQ_PRIO        10
  #define RTT_ISR             isr_rtc
  #define RTT_MAX_VALUE       (0xffffffff)
  #define RTT_FREQUENCY       (32768U)    /* in Hz. For changes see `rtt.c` */
  #define RTT_RUNSTDBY        (1)         /* Keep RTT running in sleep states */
  /** @} */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CONF_H */
  /** @} */