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-- Company: 
-- Engineer: 
-- 
-- Create Date: 08.10.2023 15:22:15
-- Design Name: 
-- Module Name: Generic unsigned full Adder  - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Adder_Generic is
    generic( N : Integer := 256);
  Port ( 
    clk_in, reset : in std_logic;
    a_in, b_in : in std_logic_vector(N-1 downto 0);
    s_out : out std_logic_vector(N downto 0)
  );
end Adder_Generic;
-- 
architecture Behavioral of Adder_Generic is
signal ain_add   : signed(N downto 0);
signal bin_add   : signed(N downto 0);
signal s_out_d    : signed(N downto 0);
begin
    s_out_d <= ain_add + bin_add;
    process(clk_in, reset)
    begin
        if reset = '1' then
            s_out <= (others => '0');
        elsif rising_edge(clk_in) then
            ain_add <= resize(signed(a_in),N+1);  
            bin_add <= resize(signed(b_in),N+1);   
            s_out   <= std_logic_vector(s_out_d);
        end if;
    end process;
end Behavioral;