From 71388fd5c75f285ae02833501290a824e5b87093 Mon Sep 17 00:00:00 2001 From: bilalelhasnaoui Date: Tue, 24 Oct 2023 18:02:31 +0200 Subject: [PATCH] seance 2 --- Exercice_1/Asynchrone_64Bits.png | Bin 0 -> 166081 bytes Exercice_1/Asynchronous_Reset.vhd | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Exercice_1/README.md | 0 Exercice_1/Synchrone_64Bits.png | Bin 0 -> 162467 bytes Exercice_1/Synchronous_Reset.vhd | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Exercice_2/RAM_Memory_ReadWrite_256Bits.png | Bin 0 -> 170949 bytes Exercice_2/RAM_ReadWrite.vhd | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Exercice_2/README.md | 0 Exercice_2/ROM_Infering.vhd | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Exercice_2/ROM_Memory_32CaseMemoire_8Bits.png | Bin 0 -> 158986 bytes Exercice_3/InOut_Pin.vhd | 46 ++++++++++++++++++++++++++++++++++++++++++++++ Exercice_3/README.md | 0 Exercice_4/Adder_Generic.vhd | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Exercice_4/Adder_full_signed.vhd | 39 +++++++++++++++++++++++++++++++++++++++ README.md | 0 15 files changed, 385 insertions(+), 0 deletions(-) create mode 100644 Exercice_1/Asynchrone_64Bits.png create mode 100644 Exercice_1/Asynchronous_Reset.vhd create mode 100644 Exercice_1/README.md create mode 100644 Exercice_1/Synchrone_64Bits.png create mode 100644 Exercice_1/Synchronous_Reset.vhd create mode 100644 Exercice_2/RAM_Memory_ReadWrite_256Bits.png create mode 100644 Exercice_2/RAM_ReadWrite.vhd create mode 100644 Exercice_2/README.md create mode 100644 Exercice_2/ROM_Infering.vhd create mode 100644 Exercice_2/ROM_Memory_32CaseMemoire_8Bits.png create mode 100644 Exercice_3/InOut_Pin.vhd create mode 100644 Exercice_3/README.md create mode 100644 Exercice_4/Adder_Generic.vhd create mode 100644 Exercice_4/Adder_full_signed.vhd create mode 100644 README.md diff --git a/Exercice_1/Asynchrone_64Bits.png b/Exercice_1/Asynchrone_64Bits.png new file mode 100644 index 0000000..336198d Binary files /dev/null and b/Exercice_1/Asynchrone_64Bits.png differ diff --git a/Exercice_1/Asynchronous_Reset.vhd b/Exercice_1/Asynchronous_Reset.vhd new file mode 100644 index 0000000..0e885f7 --- /dev/null +++ b/Exercice_1/Asynchronous_Reset.vhd @@ -0,0 +1,57 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17.10.2023 17:47:42 +-- Design Name: +-- Module Name: Exercice_1 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Asynchronous_Reset is + generic(N : natural := 64); + Port ( + reset : in std_logic; + clk_in : in std_logic; + A : in SIGNED(N-1 downto 0); + B : in SIGNED(N-1 downto 0); + Resultat : out SIGNED(2*N -1 downto 0) + ); +end Asynchronous_Reset; + +architecture Behavioral of Asynchronous_Reset is + signal produit : signed(2*N-1downto 0); +begin +-- Reset asynchrone process. +Mlutiplier: process(clk_in, reset) + begin + if reset='1' then + produit <= (others =>'0'); + elsif rising_edge(clk_in) then + produit <= A*B; + end if; + end process; + Resultat <= produit; +end Behavioral; \ No newline at end of file diff --git a/Exercice_1/README.md b/Exercice_1/README.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Exercice_1/README.md diff --git a/Exercice_1/Synchrone_64Bits.png b/Exercice_1/Synchrone_64Bits.png new file mode 100644 index 0000000..30ea11a Binary files /dev/null and b/Exercice_1/Synchrone_64Bits.png differ diff --git a/Exercice_1/Synchronous_Reset.vhd b/Exercice_1/Synchronous_Reset.vhd new file mode 100644 index 0000000..b93539f --- /dev/null +++ b/Exercice_1/Synchronous_Reset.vhd @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: ÉCOLE POLYTECHNIQUE DE LILLE - POLYTECH LILLE. +-- Engineer: +-- +-- Create Date: 17.10.2023 17:47:42 +-- Design Name: Synchronous Reset signed generic multiplier. +-- Module Name: Synchronous RESET - Behavioral +-- Project Name: Synchronous Reset signed generic multiplier. +-- Target Devices: BASYS3 +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Synchronous_Reset is + -- Déclaration de N comme generic pour varier le nombre des bits des entrés A et B. + generic(N : natural := 64); + Port ( + reset : in std_logic; -- Déclaration du reset comme input. + clk_in : in std_logic; -- Déclaration de l'horloge. + A : in SIGNED(N-1 downto 0); -- L'entrée A sur N Bits. + B : in SIGNED(N-1 downto 0); -- L'entrée B sur N Bits + Resultat : out SIGNED(2*N -1 downto 0) -- Le résultat du produit sur 2*N Bits. + ); +end Synchronous_Reset; + +architecture Behavioral of Synchronous_Reset is + signal produit : signed(2*N-1downto 0); -- Déclarataion du signal intérmidiaire pour les calculs. +begin +-- Reset synchrone process. => liste de sensibilité du processus ne contient pas le RESET. +Mlutiplier: process(clk_in) + begin + if rising_edge(clk_in) then -- Tester si il y a un font montant sur l'horloge. + if reset='1' then -- Teseter le reset pour le remise à ZERO du système. + produit <= (others =>'0'); + else + produit <= A*B; -- Calculer le produit A*B a l'aide du bibliothéque IEEE.NUMERIC_STD + end if; + end if; + end process; + Resultat <= produit; -- Affectation du signal a la résultat. +end Behavioral; \ No newline at end of file diff --git a/Exercice_2/RAM_Memory_ReadWrite_256Bits.png b/Exercice_2/RAM_Memory_ReadWrite_256Bits.png new file mode 100644 index 0000000..edfeffb Binary files /dev/null and b/Exercice_2/RAM_Memory_ReadWrite_256Bits.png differ diff --git a/Exercice_2/RAM_ReadWrite.vhd b/Exercice_2/RAM_ReadWrite.vhd new file mode 100644 index 0000000..a5a5f38 --- /dev/null +++ b/Exercice_2/RAM_ReadWrite.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- Company: ÉCOLE POLYTECHNIQUE DE LILLE +-- Engineer: +-- +-- Create Date: 19.10.2023 15:35:32 +-- Design Name: Random Access Memory Read Write. +-- Module Name: RAM_ReadWrite - Behavioral +-- Project Name: Random Access Memory Read Write. +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; -- Utilisation de NUMERIC_STD pour faire la conversion std_logic_vector to integer. +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity RAM_ReadWrite is + generic( + Address_Bits : positive :=8; -- Declaration de nombre des Bits de l'adress mémoire 8Bits => 256 case mémoire. + Data_Bits : positive :=8 -- Déclaration de nombre des Bits des données. + ); + Port ( + clk_in, Read_en, Write_en : std_logic; -- Le signal d'horloge, Enable lecture mémoire et écriture mémoire signals + Address : in std_logic_vector(Address_Bits-1 downto 0); -- L'address pour acceder au case mémoire. + Data_in : in std_logic_vector(Data_Bits-1 downto 0); -- Les données a écrire dans le RAM. + Data_out : out std_logic_vector(Data_Bits-1 downto 0) -- Les données a lire depuis la mémoire RAM. + ); +end RAM_ReadWrite; +-- Définition de l'archéticture de l'entité RAM_ReadWrite. +architecture Behavioral of RAM_ReadWrite is +-- Déclaration de la mémoire comme un tableau de 2**Address_Bits = 256 cases mémoires. +-- Chaque case est une vecteur de 8 Btis (Data_Bits-1 donwto 0) = 8 +type RAM is array (0 to 2**Address_Bits-1) of std_logic_vector(Data_Bits-1 downto 0); +-- Déclaration d'un signal mémoire pour la manipulation de lécture et écriture. +signal memory : RAM := (others => (others => '0')); +begin + RAM_ReadWrite :process(clk_in) + begin + if(rising_edge(clk_in)) then + if(Write_en = '1') then -- Si l'option écriture de mémoire est activé on écris dans le mémoire + memory(to_integer(unsigned(Address))) <= Data_in; -- Affectation des données à la case avec (address) + end if; + if(Read_en = '1') then -- Si l'option lécture de mémoire est activé on lit dans le mémoire + Data_out <= memory(to_integer(unsigned(Address))); -- Lécriture de la case en Data_out. + end if; + end if; + end process; +end Behavioral; diff --git a/Exercice_2/README.md b/Exercice_2/README.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Exercice_2/README.md diff --git a/Exercice_2/ROM_Infering.vhd b/Exercice_2/ROM_Infering.vhd new file mode 100644 index 0000000..43c97a2 --- /dev/null +++ b/Exercice_2/ROM_Infering.vhd @@ -0,0 +1,64 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19.10.2023 16:14:20 +-- Design Name: +-- Module Name: ROM_Infering - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; -- Utilisation de NUMERIC_STD pour faire la conversion std_logic_vector to integer. +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity ROM_Infering is + generic( + Address_Bits : Integer := 5; -- Les adress mémoires sot sur 5 bits donc 32 Case mémoire. (Juste pour simplifier loading aprés). + Data_Bits : Integer := 8 -- Déclaration de nombre des Bits des données. + ); + Port ( + Read_en, clk_in : in std_logic; -- Le signal d'horloge, + address: in std_logic_vector(Address_Bits-1 downto 0); -- L'address pour acceder au case mémoire. + Data_out : out std_logic_vector(Data_Bits-1 downto 0) -- Les données a lire depuis la mémoire RAM. + ); +end ROM_Infering; + +architecture Behavioral of ROM_Infering is +-- Déclaration de la mémoire comme un tableau de 2**Address_Bits = 32 cases mémoires. +-- Chaque case est une vecteur de 8 Btis (Data_Bits-1 donwto 0) = 8 +type ROM is array (0 to 2**Address_Bits-1) of std_logic_vector(Data_Bits-1 downto 0); +-- Affectation manuelle des 32 cases mémoire avec des valeurs en Hexadécimal X"AA" ou en binaire par "00001101" example. +signal ROM_memory : ROM := (X"00",X"01",X"10",X"11",X"20",X"21",X"22",X"30", + X"31",X"32",X"33",X"40",X"41",X"42",X"43",X"44", + X"50",X"51",X"52",X"53", X"54",X"55",X"60",X"61", + X"62",X"63",X"64",X"65", X"66",X"67",X"68",X"69"); +begin + ROM_Read : process(clk_in) + begin + if(rising_edge(clk_in)) then + if Read_en = '1' then -- Si le signal d'entrées Read_enable est activé en lit a partir du mémoire. + Data_out <= ROM_memory(to_integer(unsigned(address))); + end if; + end if; + end process; +end Behavioral; diff --git a/Exercice_2/ROM_Memory_32CaseMemoire_8Bits.png b/Exercice_2/ROM_Memory_32CaseMemoire_8Bits.png new file mode 100644 index 0000000..1e76324 Binary files /dev/null and b/Exercice_2/ROM_Memory_32CaseMemoire_8Bits.png differ diff --git a/Exercice_3/InOut_Pin.vhd b/Exercice_3/InOut_Pin.vhd new file mode 100644 index 0000000..b7706fb --- /dev/null +++ b/Exercice_3/InOut_Pin.vhd @@ -0,0 +1,46 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19.10.2023 17:24:45 +-- Design Name: +-- Module Name: InOut_Pin - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity InOut_Pin is + Port ( Pin : inout STD_LOGIC); +end InOut_Pin; + +architecture Behavioral of InOut_Pin is +begin + Inout_Pin :process(Pin) + begin + if(rising_edge(Pin)) then + Pin <= '0'; + end if; + end process; +end Behavioral; \ No newline at end of file diff --git a/Exercice_3/README.md b/Exercice_3/README.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Exercice_3/README.md diff --git a/Exercice_4/Adder_Generic.vhd b/Exercice_4/Adder_Generic.vhd new file mode 100644 index 0000000..3b1daba --- /dev/null +++ b/Exercice_4/Adder_Generic.vhd @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 08.10.2023 15:22:15 +-- Design Name: +-- Module Name: Generic unsigned full Adder - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +use ieee.std_logic_unsigned.all; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; +entity Adder_Generic is + generic( N : Integer := 256); + Port ( + clk_in, reset : in std_logic; + a_in, b_in : in std_logic_vector(N-1 downto 0); + s_out : out std_logic_vector(N downto 0) + ); +end Adder_Generic; +-- +architecture Behavioral of Adder_Generic is +signal ain_add : signed(N downto 0); +signal bin_add : signed(N downto 0); +signal s_out_d : signed(N downto 0); +begin + s_out_d <= ain_add + bin_add; + process(clk_in, reset) + begin + if reset = '1' then + s_out <= (others => '0'); + elsif rising_edge(clk_in) then + ain_add <= resize(signed(a_in),N+1); + bin_add <= resize(signed(b_in),N+1); + s_out <= std_logic_vector(s_out_d); + end if; + end process; +end Behavioral; \ No newline at end of file diff --git a/Exercice_4/Adder_full_signed.vhd b/Exercice_4/Adder_full_signed.vhd new file mode 100644 index 0000000..ce5b168 --- /dev/null +++ b/Exercice_4/Adder_full_signed.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity Adder_full_signed is +generic( N : integer := 512); +port ( + i_clk : in std_logic; + i_add1 : in std_logic_vector(N-1 downto 0); + i_add2 : in std_logic_vector(N-1 downto 0); + o_sum : out std_logic_vector(N downto 0)); +end Adder_full_signed; + +architecture rtl of Adder_full_signed is + +signal r_add1 : signed(N downto 0); +signal r_add2 : signed(N downto 0); +signal w_sum : signed(N downto 0); + +begin + +-- combinatorial adder + w_sum <= r_add1 + r_add2; + +r_process : process(i_clk) +begin + if(rising_edge(i_clk)) then + + -- register input and extend sign + r_add1 <= resize(signed(i_add1),N+1); + r_add2 <= resize(signed(i_add2),N+1); + + -- register output + o_sum <= std_logic_vector(w_sum); + + end if; +end process r_process; + +end rtl; \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/README.md -- libgit2 0.21.2