71388fd5
 bilalelhasnaoui
seance 2
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.10.2023 17:24:45
-- Design Name:
-- Module Name: InOut_Pin - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InOut_Pin is
Port ( Pin : inout STD_LOGIC);
end InOut_Pin;
architecture Behavioral of InOut_Pin is
begin
Inout_Pin :process(Pin)
begin
if(rising_edge(Pin)) then
Pin <= '0';
end if;
end process;
end Behavioral;
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