71388fd5
 bilalelhasnaoui
seance 2
|
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.10.2023 17:47:42
-- Design Name:
-- Module Name: Exercice_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Asynchronous_Reset is
generic(N : natural := 64);
Port (
reset : in std_logic;
clk_in : in std_logic;
A : in SIGNED(N-1 downto 0);
B : in SIGNED(N-1 downto 0);
Resultat : out SIGNED(2*N -1 downto 0)
);
end Asynchronous_Reset;
architecture Behavioral of Asynchronous_Reset is
signal produit : signed(2*N-1downto 0);
begin
-- Reset asynchrone process.
Mlutiplier: process(clk_in, reset)
begin
if reset='1' then
produit <= (others =>'0');
elsif rising_edge(clk_in) then
produit <= A*B;
end if;
end process;
Resultat <= produit;
end Behavioral;
|