#----------------------------------------------------------- # Vivado v2019.1 (64-bit) # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 # Start of session at: Wed Oct 4 15:35:14 2023 # Process ID: 9160 # Current directory: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1 # Command line: vivado.exe -log Afficheur_7SEG.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Afficheur_7SEG.tcl -notrace # Log file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG.vdi # Journal file: C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1\vivado.jou #----------------------------------------------------------- source Afficheur_7SEG.tcl -notrace Command: link_design -top Afficheur_7SEG -part xc7a35tcpg236-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7a35tcpg236-1 INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2019.1 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] Finished Parsing XDC File [C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.srcs/constrs_1/imports/TP1/Basys-3-Master.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 662.551 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 666.586 ; gain = 375.434 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 686.492 ; gain = 19.906 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 1b472ca95 Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1200.875 ; gain = 514.383 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 1b472ca95 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1b472ca95 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: 1f526e7c3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 1f526e7c3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 5 Shift Register Optimization | Checksum: 1f526e7c3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: 1f526e7c3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 260393764 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1341.555 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 260393764 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1341.555 ; gain = 0.000 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 260393764 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: 260393764 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 24 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1341.555 ; gain = 674.969 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx Command: report_drc -file Afficheur_7SEG_drc_opted.rpt -pb Afficheur_7SEG_drc_opted.pb -rpx Afficheur_7SEG_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d171f48f Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1341.555 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b8f8806f Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.835 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 2ac1244c8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.847 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 2ac1244c8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.849 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 2ac1244c8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.850 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 2ac1244c8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.852 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 2.2 Global Placement Core WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer Phase 2.2 Global Placement Core | Checksum: 21c4ed49b Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 2 Global Placement | Checksum: 21c4ed49b Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21c4ed49b Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18a378908 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 216e3a3c1 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 216e3a3c1 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4.4 Final Placement Cleanup | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19592b163 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 Ending Placer Task | Checksum: 16b3cb9b6 Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 42 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1341.555 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1352.461 ; gain = 10.906 INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file Afficheur_7SEG_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1352.461 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file Afficheur_7SEG_utilization_placed.rpt -pb Afficheur_7SEG_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file Afficheur_7SEG_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1352.461 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: 92aaeef2 ConstDB: 0 ShapeSum: d891cac4 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 9fc16879 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1442.992 ; gain = 79.531 Post Restoration Checksum: NetGraph: 769cd3b9 NumContArr: 292494c0 Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9fc16879 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9fc16879 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1449.000 ; gain = 85.539 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16939516a Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1452.375 ; gain = 88.914 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 32 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 32 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 106a7763c Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 4 Rip-up And Reroute | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 6 Post Hold Fix | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0058997 % Global Horizontal Routing Utilization = 0.0158771 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 9.90991%, No Congested Regions. South Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions. East Dir 1x1 Area, Max Cong = 23.5294%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1453.488 ; gain = 90.027 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 131215cb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1cda4acbc Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:22 ; elapsed = 00:00:20 . Memory (MB): peak = 1455.516 ; gain = 92.055 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 55 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1455.516 ; gain = 103.055 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1455.516 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1465.422 ; gain = 9.906 INFO: [Common 17-1381] The checkpoint 'C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx Command: report_drc -file Afficheur_7SEG_drc_routed.rpt -pb Afficheur_7SEG_drc_routed.pb -rpx Afficheur_7SEG_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx Command: report_methodology -file Afficheur_7SEG_methodology_drc_routed.rpt -pb Afficheur_7SEG_methodology_drc_routed.pb -rpx Afficheur_7SEG_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/profil/Desktop/Afficheur_7SEG/Afficheur_7SEG.runs/impl_1/Afficheur_7SEG_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx Command: report_power -file Afficheur_7SEG_power_routed.rpt -pb Afficheur_7SEG_power_summary_routed.pb -rpx Afficheur_7SEG_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 67 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file Afficheur_7SEG_route_status.rpt -pb Afficheur_7SEG_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Afficheur_7SEG_timing_summary_routed.rpt -pb Afficheur_7SEG_timing_summary_routed.pb -rpx Afficheur_7SEG_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file Afficheur_7SEG_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file Afficheur_7SEG_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Afficheur_7SEG_bus_skew_routed.rpt -pb Afficheur_7SEG_bus_skew_routed.pb -rpx Afficheur_7SEG_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs Command: write_bitstream -force Afficheur_7SEG.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado 12-3199] DRC finished with 0 Errors INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Bitstream compression saved 15755616 bits. Writing bitstream ./Afficheur_7SEG.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 86 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1920.316 ; gain = 405.871 INFO: [Common 17-206] Exiting Vivado at Wed Oct 4 15:36:15 2023...